Method of manufacturing mask type read only memory

Claim 1

A method of manufacturing a mask type Read Only Memory, comprising the following steps in the following order: selectively forming a first insulating layer having a thick portion and a thin portion for a field region and a gate insulating layer, respectively, on a semiconductor substrate of a first conductivity type; forming a polysilicon layer on said insulating layer; forming gate electrodes of first and second MOS transistors by partially removing said polysilicon layer; forming second conductivity type regions to be source and drain regions of said MOS transistors in said semiconductor substrate; forming a second insulating film on said semiconductor substrate, in which the MOS transistors are formed by the source and drain regions and channel regions therebetween, said channel regions having said gate electrodes formed thereover; forming a contact hole in the second insulating film on the second conductivity type region of said second MOS transistor for allowing the formation of an outer electrode; forming the outer electrodes in said contact hole and forming bonding pads on said second insulating film; selectively removing said second insulating film and exposing the gate electrode and parts of source and drain regions of said first MOS transistor; implanting ions of said second conductivity type to the channel region and said parts of source and drain regions of said first MOS transistor; forming a protective film on said bonding pads, the outer electrodes, and the MOS transistors; removing said protective film on the bonding pad; and providing an outer-lead in contact with the bonding pad.

Claim 2

A method of manufacturing a mask type Read Only Memory, comprising the following steps in the following order: selectively forming a first insulating layer having a thick portion and a thin portion for a field region and a gate insulating layer, respectively, on a semiconductor substrate of a first conductivity type; forming a polysilicon layer on said insulating layer; forming gate electrodes of first and second MOS transistors by partially removing said polysilicon layer; forming second conductivity type regions to be source and drain regions of said MOS transistors in said semiconductor substrate; forming a second insulating film on said semiconductor substrate, in which the MOS transistors are formed by the source and drain regions and channel regions therebetween, said channel regions having said gate electrodes formed thereover; forming a contact hole in the second insulating film on the second conductivity type region of said second MOS transistor for allowing the formation of an outer electrode; forming the outer electrodes in said contact hole and forming bonding pads on said second insulating film; selectively removing said second insulating film and exposing the gate electrode and parts of source and drain regions of said first MOS transistor; implanting ions of said second conductivity type to the channel region and said parts of source and drain regions of said first MOS transistor; forming a protective film on said bonding pads, the outer electrodes, and the MOS transistors; removing said protective film on the bonding pad; and providing an outer-lead in contact with the bonding pad.