ROM memory programming procedure using MOS technology with thin gate oxide and junctions

Claim 1

ROM memory programming procedure using MOS technology with thin gate oxide and junctions in which the programming of a memory cell takes place starting with a cell already formed with source and drain junctions made in a substrate between adjacent field oxide areas, a thin layer of gate oxide overlain on the substrate between said field oxide areas, and a stirp of polycrystalline silicon gate overlain on said gate oxide and incorporated in an oxide layer subsequently grown spanning the zone between said junctions characterized in that it comprises the phases of wet isotropic etching of the cell area for removal of the oxide above, beside and partially underneath said strip of polycrystalline silicon, implantation of dopant of a type opposite to that of the source junction and drain junction through said strip of polycrystalline silicon, in the zone of the substrate underlying said strip, and reoxidation of the entire cell area.