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JPS5447489A Expired / Lapsed JP ⏱️ 0.0 years remaining

Production of mos semiconductor device

Assignee: Hitachi Ltd
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Filing: 1977-09-21
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Granted: —
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Expires: 1997-09-21
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Abstract

Abstract PURPOSE: To minimize spacing by forming poly-Si gates of eaves form or a negative grade and providing source and drain electrodes through self-alignment. CONSTITUTION: A field oxide film 2 and a gate oxide film 3 are provided on an n type Si substrate 1 and poly-si 4 is deposited. The side faces of the poly-Si gate 4a are deeply removed (d) by gas plasma etching through a resist mask 5. After p ions are implanted, the film 3 is etched away and Al is evaportated, then the conductor layers 6a, 6b are isolatedly formed because of the eaves part. Next, the reist is lifted off to remove the layer 6b, and p ions are supplementarily implanted and annealed, after which an Al layer 8 is formed. In this way the gate electrodes as well as source and drain electrodes may be formed at the shortest distance in a self-alignment manner COPYRIGHT: (C)1979,JPO&Japio

Inventors

  • 👤 Yasunobu Osa
  • 👤 Yukio Tanigaki

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-28 00:13
CPC Classifications
—

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