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US4649629A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of late programming a read only memory

Assignee: STMicroelectronics lnc USA
•
Filing: 1985-07-29
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Granted: 1987-03-17
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Expires: 2005-07-29
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Abstract

Abstract Transistors (10) having lateral gaps between their source and drain and the gate are interconnected in a ROM to receive program code. In one embodiment of the invention (FIG. 3), the gaps of selected transistors (42) are subjected to a phosphorous implant (44) to create lightly doped n - regions (26,28) connecting the source (18) and drain (20) to the gate (14), and function normally. The other transistors (40) do not receive the phosphorous implant, and thus have a higher threshold voltage. In another embodiment of the invention (FIG. 2) all of the transistors receive the phosphorous implant to create the n - regions (26,28) connecting the source and drain to the gate, and the n - regions of selected transistors (32) are counter-doped with a boron implant (34) so as to raise their threshold voltages, while the other transistors (30) are not counter-doped and function normally. In both embodiments, programming can occur late in the processing of the ROM.

Inventors

  • 👤 Robert O. Miller
  • 👤 Dale A. Simpson

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 19:41
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/387; H10B20/34; H10B20/36; Y; Y10; Y10S; Y10S148/00; Y10S148/082

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 155 words
A method of ROM manufacture copmprising the sequential steps of: forming in a common substrate a plurality of transistors, each including first and second regions of one conductivity type spaced apart by an intermediate region of the opposite conductivity type, each of the first and second regions including a more heavily doped main portion and a less heavily doped lateral gap portion, said gap portion lying between the main portion and the intermediate region, and a gate electrode overlying the surface portion of the intermediate region and not overlying the gap portion of the first and second regions, masking selected transistors according to a desired programming code, and subjecting the plurality of transistors to an implant of ions of the type characteristic of said opposite conductivity type sufficient to convert said gap portions of the first and second regions of the unmasked transistors to said opposite conductivity type, whereby said unmasked transistors are effectively disabled.
Claim 2
Independent Claim 155 words
A method of ROM manufacture copmprising the sequential steps of: forming in a common substrate a plurality of transistors, each including first and second regions of one conductivity type spaced apart by an intermediate region of the opposite conductivity type, each of the first and second regions including a more heavily doped main portion and a less heavily doped lateral gap portion, said gap portion lying between the main portion and the intermediate region, and a gate electrode overlying the surface portion of the intermediate region and not overlying the gap portion of the first and second regions, masking selected transistors according to a desired programming code, and subjecting the plurality of transistors to an implant of ions of the type characteristic of said opposite conductivity type sufficient to convert said gap portions of the first and second regions of the unmasked transistors to said opposite conductivity type, whereby said unmasked transistors are effectively disabled.
Claim 3
Dependent Claim 72 words
The method of claim 1, in which the transistors are initially formed so that in each transistor the intermediate region of opposite conductivity type includes halo portions of higher doping of the like conductivity type which underlie the gap portions of the first and second regions and said ion implant is sufficient to convert essentially entirely the gap portions overlying said halo regions of the unmasked transistors to said opposite conductivity type.
Claim 4
Dependent Claim 25 words
The method of claim 1, in which the first and second regions are n-type, the intermediate region p-type and the implant is of boron ions.

References Cited (Backward Citations)

US4472871A Cited
US4376947A Cited
US4406049A Cited
US4419809A Cited
US4455742A Cited
US4545110A Cited
US4536944A Cited
US4488351A Cited
US4513494A Cited
US4590665A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-03-16 1990-09-15 1991-03-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-03-16 1994-09-15 1995-03-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-03-16 1998-09-15 1999-03-17 $7700.00 Window Closed / Lapsed

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