US5336624A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for disguising a microelectronic integrated digital logic
Assignee: The AT&T MVPD Group LLC
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Filing: 1992-12-07
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Granted: 1994-08-09
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Expires: 2012-12-07
Abstract
Abstract Focussed ion beam (FIB) implants (38,40) are used to set the threshold voltages of metal-oxide-semiconductor field-effect transistors (MOSFETs) in a selected logic gate (34,36) in a microelectronic integrated digital logic circuit (31) such that the direct current (DC) transfer function and logic thresholds are essentially the same as for another logic gate (30,32) which is not altered by FIB implants, but the switching speed is greatly reduced. This causes the altered gate (34,36) to switch in an apparently normal manner when tested under DC or low speed conditions, but to not switch at normal operating speed. The altered or disguised gate (34,36) is thereby always on or always off at the normal operating speed, whereas the unaltered gate (30,32) switches in the normal manner. This impedes attempts at reverse engineering since the circuit (31) operates differently under test and operating conditions, and the true logic functions of the gate (34,36) cannot be determined by known low speed test procedures.
Inventors
- 👤 Robert H. Walden
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:23
CPC Classifications
H; H10; H10D; H10D89/00
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
245 words
A method of fabricating a microelectronic integrated digital logic circuit designed to operate at an operating switching speed so that the circuit is resistant to reverse engineering testing performed at a test switching speed that is slower than said operating switching speed, comprising the steps of: (a) forming a first microelectronic digital switching element on a substrate, the first switching element including a first field-effect transistor (FET) having a first channel with a first doping concentration which produces a corresponding first threshold voltage for said first switching element, and a corresponding first switching speed capability for said first switching element which is higher than said operating switching speed; and (b) forming a second microelectronic digital switching element which is connected in a logic circuit with the first switching element on the substrate, the second switching element including a second FET having a second channel with a second doping concentration which produces a corresponding second threshold voltage for said second switching element, and a corresponding second switching speed capability for said second switching element which is slower than said operating switching speed, slower than the first switching element's switching speed capability, but faster than said test switching speed; the first and second switching element both being capable of switching at said test switching speed, but only the first switching element being capable of switching at the operating switching speed, such that the circuit operates differently at the test switching speed than at the operating switching speed.
Claim 2
Independent Claim
245 words
A method of fabricating a microelectronic integrated digital logic circuit designed to operate at an operating switching speed so that the circuit is resistant to reverse engineering testing performed at a test switching speed that is slower than said operating switching speed, comprising the steps of: (a) forming a first microelectronic digital switching element on a substrate, the first switching element including a first field-effect transistor (FET) having a first channel with a first doping concentration which produces a corresponding first threshold voltage for said first switching element, and a corresponding first switching speed capability for said first switching element which is higher than said operating switching speed; and (b) forming a second microelectronic digital switching element which is connected in a logic circuit with the first switching element on the substrate, the second switching element including a second FET having a second channel with a second doping concentration which produces a corresponding second threshold voltage for said second switching element, and a corresponding second switching speed capability for said second switching element which is slower than said operating switching speed, slower than the first switching element's switching speed capability, but faster than said test switching speed; the first and second switching element both being capable of switching at said test switching speed, but only the first switching element being capable of switching at the operating switching speed, such that the circuit operates differently at the test switching speed than at the operating switching speed.
Claim 3
Dependent Claim
58 words
A method as in claim 1, in which: steps (a) and (b) in combination comprise the substeps of: (c) partially forming the first and second FETs simultaneously and integrally such that the respective first and second channels both have the first doping concentration; and (d) increasing the doping concentration of the second channel to said second doping concentration.
Claim 4
Dependent Claim
17 words
A method as in claim 2, in which step (d) comprises implanting ions into the second channel.
Claim 5
Dependent Claim
78 words
A method as in claim 1, further comprising the step of: (c) further forming the second switching element as including a third FET which is connected in circuit with the second FET to constitute an active load, the third FET having a third channel with a third doping concentration which produces a corresponding third threshold voltage such that the second and third threshold voltages are different from the second switching voltage by opposite and approximately equal voltages respectively.
Claim 6
Dependent Claim
25 words
A method as in claim 4, in which step (c) comprises forming the third FET such that the active load is a depletion mode load.
Claim 7
Dependent Claim
24 words
A method as in claim 5, in which steps (b) and (c) comprise forming the second and third FETs as n-channel metal-oxide-semiconductor (NMOS) FETs.
Claim 8
Dependent Claim
126 words
A method as in claim 1, in which: step (b) comprises forming the second FET as a complementary metal-oxide-semiconductor (CMOS) FET of a first conductivity type; and the method further comprises the step of: (c) forming the second switching element as further including a third FET which is a CMOS FET of a second conductivity type which is opposite to the first conductivity type, the third FET being connected in circuit with the second FET such that the second switching element is a CMOS element, the third FET having a third channel with a third doping concentration which produces a corresponding third threshold voltage such that the second and third threshold voltages are different from the second switching voltage by opposite and approximately equal voltages respectively.
Claim 9
Dependent Claim
122 words
A method as in claim 1, in which: step (b) comprises forming the second FET as a complementary metal-oxide-semiconductor (CMOS) FET of a first conductivity type; and the method further comprises the step of: (c) forming the second switching element as further including a third FET which is a CMOS FET of a second conductivity type which is opposite to the first conductivity type, the third FET being connected in circuit with the second FET such that the second switching element is a CMOS element, the third FET having a third channel with a third doping concentration which produces a corresponding third threshold voltage, the second and third threshold voltages being selected to cause subthreshold operation of the second and third FETs.
Claim 10
Independent Claim
197 words
A method of fabricating a microelectronic integrated digital logic circuit designed to operate at an operating switching speed so that the circuit is resistant to reverse engineering testing performed at a test switching speed that is slower than said operating switching speed, comprising the steps of: (a) forming first and second microelectronic digital switching elements on a substrate, said first and second switching elements including respective first and second field-effect transistors (FETs) having respective first and second channels with equal doping concentrations which produce equal threshold voltages and equal switching speed capabilities for said first and second switching elements, said switching speed capabilities being higher than said operating switching speed; and (b) thereafter altering the doping concentration of said second FET so that its switching speed capability is reduced to a speed slower than said operating switching speed but faster than said test switching speed; the first switching element and the altered second switching element both being capable of switching at said test switching speed, but only the first switching element being capable of switching at the operating switching speed, such that the circuit operates differently at the test switching speed than at the operating switching speed.
Claim 11
Independent Claim
197 words
A method of fabricating a microelectronic integrated digital logic circuit designed to operate at an operating switching speed so that the circuit is resistant to reverse engineering testing performed at a test switching speed that is slower than said operating switching speed, comprising the steps of: (a) forming first and second microelectronic digital switching elements on a substrate, said first and second switching elements including respective first and second field-effect transistors (FETs) having respective first and second channels with equal doping concentrations which produce equal threshold voltages and equal switching speed capabilities for said first and second switching elements, said switching speed capabilities being higher than said operating switching speed; and (b) thereafter altering the doping concentration of said second FET so that its switching speed capability is reduced to a speed slower than said operating switching speed but faster than said test switching speed; the first switching element and the altered second switching element both being capable of switching at said test switching speed, but only the first switching element being capable of switching at the operating switching speed, such that the circuit operates differently at the test switching speed than at the operating switching speed.
Claim 12
Dependent Claim
78 words
A method as in claim 9, further comprising the step of: (c) further forming the second switching element as including a third FET which is connected in circuit with the second FET to constitute an active load, the third FET having a third channel with a third doping concentration which produces a corresponding third threshold voltage such that the second and third threshold voltages are different from the second switching voltage by opposite and approximately equal voltages respectively.
Claim 13
Dependent Claim
25 words
A method as in claim 10, in which step (c) comprises forming the third FET such that the active load is a depletion mode load.
Claim 14
Dependent Claim
24 words
A method as in claim 11, in which steps (b) and (c) comprise forming the second and third FETs as n-channel metal-oxide-semiconductor (NMOS) FETs.
Claim 15
Dependent Claim
126 words
A method as in claim 9, in which: step (b) comprises forming the second FET as a complementary metal-oxide-semiconductor (CMOS) FET of a first conductivity type; and the method further comprises the step of: (c) forming the second switching element as further including a third FET which is a CMOS FET of a second conductivity type which is opposite to the first conductivity type, the third FET being connected in circuit with the second FET such that the second switching element is a CMOS element, the third FET having a third channel with a third doping concentration which produces a corresponding third threshold voltage such that the second and third threshold voltages are different from the second switching voltage by opposite and approximately equal voltages respectively.
Claim 16
Dependent Claim
122 words
A method as in claim 9, in which: step (b) comprises forming the second FET as a complementary metal-oxide-semiconductor (CMOS) FET of a first conductivity type; and the method further comprises the step of: (c) forming the second switching element as further including a third FET which is a CMOS FET of a second conductivity type which is opposite to the first conductivity type, the third FET being connected in circuit with the second FET such that the second switching element is a CMOS element, the third FET having a third channel with a third doping concentration which produces a corresponding third threshold voltage, the second and third threshold voltages being selected to cause subthreshold operation of the second and third FETs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |