US4922136A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Master slice integrated circuit having high and low speed unit cells
Assignee: Mitsubishi Electric Corp
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Filing: 1988-08-15
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Granted: 1990-05-01
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Expires: 2008-08-15
Abstract
Abstract A semiconductor integrated circuit of the master slice system is formed by arranging internal cell groups of different operating speeds in the form of arrays respectively. The internal cell groups of different operating speeds can be interconnected with each other through internal connecting areas, to reduce power consumption. The structure of each internal cell group can be optimized in accordance with its operating speed, so that the entire formation area is not much increased. Further, the formation ratio of the internal cell groups of different operating speeds is so appropriately set as to improve availability thereof.
Inventors
- 👤 Masahiro Ueda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 00:16
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/901; H03; H03K; H03K19/00; H03K19/003; H03K19/00323; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
135 words
A semiconductor integrated circuit of the master slice system, comprising: a semiconductor chip; a first internal cell group formed on said semiconductor chip, said first internal cell group including a plurality of first internal cells having a first operating speed; a second internal chip group formed on said semiconductor chip, said second internal cell group including a plurality of second internal cells having a second operating speed which is different from said first operating speed, wherein said first and second internal cells are arranged in the form of arrays, respectively wherein first operating speed of said first internal cells is relatively high and said second operating speed of said second internal cells is relatively low and wherein the numbers of said first internal cells and said second internal cells are in the ratio of 1:10.
Claim 2
Dependent Claim
135 words
A semiconductor integrated circuit of the master slice system, comprising: a semiconductor chip; a first internal cell group formed on said semiconductor chip, said first internal cell group including a plurality of first internal cells having a first operating speed; a second internal chip group formed on said semiconductor chip, said second internal cell group including a plurality of second internal cells having a second operating speed which is different from said first operating speed, wherein said first and second internal cells are arranged in the form of arrays, respectively wherein first operating speed of said first internal cells is relatively high and said second operating speed of said second internal cells is relatively low and wherein the numbers of said first internal cells and said second internal cells are in the ratio of 1:10.
Claim 3
Dependent Claim
35 words
A semiconductor integrated circuit in accordance with claim 1, further including interconnection area formed around said first internal cell group and said second internal cell group commonly to said first and second internal cell groups.
Claim 4
Dependent Claim
20 words
A semiconductor integrated circuit in accordance with claim 2, further including an input/output buffer region formed around said interconnection area.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-30 | 1993-10-30 | 1994-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-30 | 1997-10-30 | 1998-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-30 | 2001-10-30 | 2002-05-01 | $7700.00 | Window Closed / Lapsed |