Transistor integrated device, particularly usable for coding purposes

Claim 2

A logic integrated circuit comprising: input conductors; a plurality of logic gate means, each having at least one input and an output, and being interconnected with said input conductors; an output terminal connected to the output of one of the logic gate means; said logic gate means including active logic gate means, and passive logic gate means which are either short circuits or open circuits, said active logic gate means and passive logic gate means being visually indistinguishable from each other as a result of different dopant levels; whereby the physical observation of the logic means does not reveal the logic combination provided between said input conductors and said output terminal.

Claim 3

A circuit according to claim 1, further comprising a shift register having a serial input terminal, at least certain cells of the shift register being connected to said input conductors.

Claim 4

A circuit according to claim 2, wherein each of the input conductors is connected to a respective cell of the shift register.

Claim 5

A circuit according to claim 3, wherein said logic gate means includes: serially connected active and passive logic gate means, said passive logic gate means providing a permanent conductive circuit path, the first of said serially connected logic gate means connected to one of said input conductors, and the last of said serially connected logic gate means connected to said output terminal; parallel connected logic gate means, each of said parallel connected gate means having an input connected to a different one of said input conductors, and an output connected to a second input of one of said serially connected gate means; whereby said output terminal provides a coded output signal in response to a signal applied to said shift register, said parallel and serial logic gate means providing decoding of said shift register contents through visually indistinguishable passive and active logic gate means.

Claim 6

A circuit according to claim 4 wherein the active logic gate means of said serially connected logic gate means are exclusive -OR gates.

Claim 7

A circuit according to claim 4 wherein all of said parallel connected logic gate means are passive, being either short circuits, or open circuits.

Claim 8

A circuit according to claim 6 wherein the passive of said serially connected logic gate means have their second input connected to the output of the parallel connected logic gate means which are open circuits.

Claim 9

A circuit according to claim 1 wherein said logic gate means comprises MOS transistors, in which a different doping results in producing active transistors or passive transistors, said passive transistors being either short circuits or open circuits between their source and drain electrodes.

Claim 10

A circuit according to claim 8 wherein certain of the passive transistors have undoped regions.

Claim 11

A circuit according to claims 2, 3, 4, 5, 6 or 7 further comprising means enclosing said combinational logic integrated circuit to define a transaction card intended for carring out a transaction with a terminal, information exchange between the card and the terminal passing through said logic circuit.

Claim 12

An MOS logic integrated circuit comprising: first and second input terminals E1, E2 adapted to receive respective logic signals relative to a common ground connection; an output terminal; first and second inverting MOS transistors having gates directly coupled to said first and second inputs, said transistors delivering as outputs inverted signals from said first and second inputs, respectively; first and second processing MOS transistors having gates coupled to receive signals from said first input and to receive said inverted second input signal, respectively; third and fourth processing MOS transistors having gates coupled to receive said inverted first input signal and to receive signals from said second input, respectively; the source-drain paths of said first and secondprocessing MOS transistors being serially arranged with those of said third and fourth processing MOS transistors between said output terminal and a ground connection; fifth and sixth processing MOS transistors arranged in source-drain parallel relationship and having gates coupled to said first input and to receive said inverted second input signal, respectively; seventh and eighth processing MOS transistors having gates coupled to receive said inverted first input signal and to receive a signal from said second input, respectively; the source-drain paths of said fifth and sixth processing MOS transistors being serially arranged with those of said seventh and eighth processing MOS transistors between said output terminal and ground connection; at least one of said processing transitors being doped to be passive and inactive in response to its gate signal.

Claim 13

An MOS logic integrated circuit comprising: first and second input terminals E1, E2 adapted to receive respective logic signals relative to a common ground connection; an output terminal; first and second inverting MOS transistors having gates directly coupled to said first and second inputs, said transistors delivering as outputs inverted signals from said first and second inputs, respectively; first and second processing MOS transistors having gates coupled to receive signals from said first input and to receive said inverted second input signal, respectively; third and fourth processing MOS transistors having gates coupled to receive said inverted first input signal and to receive signals from said second input, respectively; the source-drain paths of said first and secondprocessing MOS transistors being serially arranged with those of said third and fourth processing MOS transistors between said output terminal and a ground connection; fifth and sixth processing MOS transistors arranged in source-drain parallel relationship and having gates coupled to said first input and to receive said inverted second input signal, respectively; seventh and eighth processing MOS transistors having gates coupled to receive said inverted first input signal and to receive a signal from said second input, respectively; the source-drain paths of said fifth and sixth processing MOS transistors being serially arranged with those of said seventh and eighth processing MOS transistors between said output terminal and ground connection; at least one of said processing transitors being doped to be passive and inactive in response to its gate signal.

Claim 14

An MOS logic integrated circuit according to claim 11 wherein said passive transistor structure provides a short circuit.

Claim 15

An MOS logic integrated circuit according to claim 11 wherein said passive transistor structure defines an open circuit.

Claim 16

An MOS logic integrated circuit according to claim 11 wherein at least said first and fourth processing transistor are active, and at least said second and third processing transistor structures are open circuits, so as to define a NAND gate, the path through said fifth to eighth processing transistors comprising at least one open circuit transistor.

Claim 17

An MOS logic integrated circuit according to claim 11 wherein said first and second inverting transistors are active, at least said second and third processing transistors are active, at least said first and fourth processing transistors are open circuits so as to define an OR gate, and the path through said fifth to eighth processing transistors comprise at least two open circuit transistors.

Claim 18

An MOS logic integrated circuit according to claim 11 wherein at least one of said third and fourth and of said fifth and sixth processing transistors are short circuits, and said second and seventh processing transistors are passive open circuits, and the remaining transistors being active, so as to define a NOR gate.

Claim 19

An MOS logic integrated circuit according to claim 11 wherein said first and second inverting transistors are active, as well as the third and sixth processing transistors, the other transistors being passive and arranged for paralleling the third and sixth processing between the output terminal and the ground, so as to define an AND gate.

Claim 20

An MOS logic integrated circuit according to claim 11 wherein at least one of said third and fourth processing transistors is a short circuit, said fifth to eighth processing transistors being connected to define an open circuit, and the second processing transistors constitutes an open circuit whereby a NEGATION gate is defined.

Claim 21

An MOS logic integrated circuit according to claim 11 wherein at least one of said first and second processing transistors is a short circut, said fifth to eighth processing transistors being connected to define an open circuit, and the fourth transitor being an open circuit, whereby an EQUAL gate is formed.

Claim 22

An MOS logic integrated circuit according to claim 11 wheren said first, fourth, sixth and seventh processing transistors are open circuits whereby an EXCLUSIVE -OR gate is formed.

Claim 23

An MOS logic integrated circuit according to claim 11, wherein at least one of said third and fourth and of said fifth and sixth processing transistors are short circuits so as to define a logic FALSE gate.

Claim 24

An MOS logic integrated circuit according to claim 11 wherein the second, fourth, fifth and seventh processing transistors are open circuits so as to define a logical TRUE gate.

Claim 25

A logic integrated circuit of claim 1 wherein said logic gate means comprises: a pair of transistors for providing inverted signals from a pair of said input conductors; first and second MOS transistor means having respective gates, said first MOS transistor means gate connected to receive signals from one conductor of said conductor pair, said second MOS transistor means gate connected to receive an inverted signal of a remaining conductor of said conductor pair; third and fourth MOS transistor means having respective gates, said third MOS transistor means having a gate coupled to receive said inverted signal from said one conductor of said pair, and said fourth MOS transistor means having a gate connected to receive a signal from said remaining conductor, said first and second transistor means having source-drain connections in series respectively with said third and fourth transistor means source-drain connections; fifth and sixth MOS transistor means, said fifth MOS transistor means having a gate coupled to receive a signal from said one conductor, and said sixth MOS transistor means having a gate connected to receive an inverted signal from said remaining conductor; seventh and eighth MOS transistor means, said seventh MOS transistor means having a gate connected to receive an inverted signal from said one conductor, said eight MOS transistor means having a gate connected to receive a signal from said second input; said fifth and sixth MOS transistor means having respective source-drain connections serially connected to said seventh and eighth MOS transistor means; at least one of said MOS transistor means being doped to include at least one passive transistor visually undistinguishable from remaining transistors in said MOS transistor means.