US4268950A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Post-metal ion implant programmable MOS read only memory
Assignee: Texas Instruments Inc
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Filing: 1978-06-05
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Granted: 1981-05-26
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Expires: 1998-06-05
Abstract
Abstract An MOS read only memory, or ROM, is formed by a process compatible with standard silicon gate manufacturing methods. The ROM is programmed either after the top level of device interconnects has been patterned and sintered, usually the last step in the slice processing method before electrical testing of the devices, or after the electrical testing of the devices. All potential MOS transistors in the ROM array are initially at a logic "0" or a logic "1". Selected transistors are programmed by implanting ions of the appropriate impurity type through their gates and gate oxides into the silicon, using photoresist as an implant mask. Impurities are electrically activated by laser annealing, and residual oxide charge is removed by rf plasma anneal.
Inventors
- 👤 Pallab K. Chatterjee
- 👤 Al F. Tasch, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 02:34
CPC Classifications
H; H10; H10P; H10P34/00; H10P34/40; H10P34/42; H10B; H10B20/00; Y; Y10; Y10S; Y10S438/00; Y10S438/91
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
95 words
A method of making a read-only-memory comprising the steps of: forming a plurality of insulated gate field effect transistors in a face of a semiconductor body, each of said transistors having a source, a drain and a gate, said transistors being in a regular pattern to provide an array of memory cells; and programming the array of memory cells by masked ion implant through the gate and gate insulator into said semiconductor body beneath selected ones of said transistors, laser annealing to activate said implanted ions, and r.f. annealing to eliminate implant induced interface charge.
Claim 2
Independent Claim
95 words
A method of making a read-only-memory comprising the steps of: forming a plurality of insulated gate field effect transistors in a face of a semiconductor body, each of said transistors having a source, a drain and a gate, said transistors being in a regular pattern to provide an array of memory cells; and programming the array of memory cells by masked ion implant through the gate and gate insulator into said semiconductor body beneath selected ones of said transistors, laser annealing to activate said implanted ions, and r.f. annealing to eliminate implant induced interface charge.
Claim 3
Dependent Claim
50 words
A method according to claim 1 wherein a plurality of other transistors and a plurality of contacts and interconnections are formed on said face peripheral to said array, wherein said step of programming uses a mask comprising a coating of photoresist applied after said contacts and interconnections have been formed.
Claim 4
Dependent Claim
38 words
A method according to claim 2, wherein the said field effect transistors and said other transistors are n-channel silicon gate transistors, and wherein said contacts and interconnections are formed by metal deposited in a thin film and patterned.
Claim 5
Independent Claim
78 words
A method of making a semiconductor device comprising the steps of: forming a plurality of circuit elements in a face of a semiconductor body, each of said circuit elements having electrodes in said face and a control electrode overlying said face; and changing the characteristics of the circuit elements by masked ion implant through the control electrode into the semiconductor body beneath, laser annealing to activate the implanted impurity, and r.f. annealing to eliminate implant induced interface charge.
Claim 6
Independent Claim
78 words
A method of making a semiconductor device comprising the steps of: forming a plurality of circuit elements in a face of a semiconductor body, each of said circuit elements having electrodes in said face and a control electrode overlying said face; and changing the characteristics of the circuit elements by masked ion implant through the control electrode into the semiconductor body beneath, laser annealing to activate the implanted impurity, and r.f. annealing to eliminate implant induced interface charge.
Claim 7
Dependent Claim
11 words
A method according to claim 3 wherein said ions are p-type.
Claim 8
Dependent Claim
11 words
A method according to claim 3 wherein said metal is aluminum.
Claim 9
Dependent Claim
17 words
A method according to claim 1 wherein said implant penetrates through an insulating layer overlying said gate.
Claim 10
Dependent Claim
41 words
A method according to claim 4, wherein a plurality of contacts and interconnections are formed on said face, and wherein said step of changing uses a mask comprising a coating of photoresist applied after said contacts and interconnections have been formed.
Claim 11
Dependent Claim
14 words
A method according to claim 8, wherein said circuit elements are field effect transistors.
Claim 12
Dependent Claim
18 words
A method according to claim 4 wherein said implant penetrates through an insulating layer overlying said control electrode.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-05-25 | 1984-11-24 | 1985-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-05-25 | 1988-11-24 | 1989-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-05-25 | 1992-11-24 | 1993-05-26 | $7700.00 | Window Closed / Lapsed |