Patent US5229311A successfully refreshed from Google Patents.
US5229311A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of reducing hot-electron degradation in semiconductor devices
Assignee: Intel Corp
•
Filing: 1992-03-25
•
Granted: 1993-07-20
•
Expires: 2012-03-25
Abstract
Abstract A method of reducing the degradation effects associated with avalanche injection or tunnelling of hot-electrons in a field-effect semiconductor device is disclosed. The method of the present invention includes covering the active regions of the semiconductor device with a protective titanium barrier layer which is deposited directly underneath the ordinary metalization layers used for connecting the devices to bit and word lines within an array. Inclusion of the titanium barrier layer in a flash memory device results in a substantial improvement in the erasetime push-out and reduces excess charge loss normally associated with hot-electron devices.
Inventors
- 👤 Stefan K. Lai
- 👤 Daniel N. Tang
- 👤 Simon Y. Wang
- 👤 Susan L. Kao
- 👤 Baylor B. Triplett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:58
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/425; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D62/00; H10D62/80; H10D62/83; H10D64/00; H10D64/60; H10D64/62
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
83 words
A method of forming an interconnecting layer in a field-effect semiconductor device, said device having a channel region, a source region, and a drain region, said method comprising the steps of: (a) depositing a barrier layer over a semiconductor substrate, said barrier layer having an affinity for hydrogen; (b) depositing a metal layer over said barrier layer; and (c) patterning said barrier layer such that said barrier layer adequately overlies said channel, said source and said drain regions to block and/or getter hydrogen.
Claim 2
Independent Claim
83 words
A method of forming an interconnecting layer in a field-effect semiconductor device, said device having a channel region, a source region, and a drain region, said method comprising the steps of: (a) depositing a barrier layer over a semiconductor substrate, said barrier layer having an affinity for hydrogen; (b) depositing a metal layer over said barrier layer; and (c) patterning said barrier layer such that said barrier layer adequately overlies said channel, said source and said drain regions to block and/or getter hydrogen.
Claim 3
Dependent Claim
15 words
The method of claim 1 wherein said barrier layer comprises a compound which includes titanium.
Claim 4
Dependent Claim
22 words
The method of claim 1 wherein said barrier layer is selected from the group consisting of titanium, titanium nitride, and titanium tungsten.
Claim 5
Dependent Claim
15 words
The method of claim 3, wherein said barrier layer is greater than 100 Å thick.
Claim 6
Dependent Claim
100 words
The method of claim 1 further comprising the steps of: forming a silicon dioxide layer over said substrate prior to the step of depositing said barrier layer; forming a gate member over said silicon dioxide layer; and forming a source region and a drain region within said substrate before depositing said barrier layer, wherein said source region and said drain region define said channel region, and wherein said barrier layer adequately overlies said source, said drain and said channel regions to block and/or getter hydrogen and said interconnecting layer makes electrical contact to said source region and/or said drain region.
Claim 7
Dependent Claim
23 words
The method of claim 1 wherein said barrier layer underlies a passivation layer over said channel region, said passivation layer comprising silicon oxynitride.
Claim 8
Dependent Claim
29 words
The method of claim 1, wherein said interconnecting layer makes electrical contact with electrically programmable and electrically erasable memory cells within a memory array of a flash memory device.
Claim 9
Dependent Claim
22 words
The method of claim 7, wherein said barrier layer is selected from the group consisting of titanium, titanium nitride; and titanium tungsten.
Claim 10
Dependent Claim
15 words
The method of claim 8, wherein said barrier layer is greater than 100 Å thick.
Claim 11
Dependent Claim
34 words
The method of claim 7 wherein said barrier layer adequately overlies said channel, said source, and said drain regions to block and/or getter hydrogen of each of said memory cells in said memory array.
Claim 12
Dependent Claim
23 words
The method of claim 10 wherein said barrier layer underlies a passivation layer over said channel region, said passivation layer comprising silicon oxynitride.
Claim 13
Dependent Claim
15 words
The method of claim 7, wherein said barrier layer comprises a compound which includes titanium.
Claim 14
Dependent Claim
23 words
The method of claim 12 wherein said barrier layer underlies a passivation layer over said channel region, said passivation layer comprising silicon oxynitride.
Claim 15
Dependent Claim
34 words
The method of claim 12 wherein said barrier layer adequately overlies said channel, said source, and said drain regions to block and/or getter hydrogen of each of said memory cells in said memory array.
Claim 16
Dependent Claim
23 words
The method of claim 14 wherein said barrier layer underlies a passivation layer over said channel region, said passivation layer comprising silicon oxynitride.
Claim 17
Dependent Claim
23 words
The method of claim 7 wherein said barrier layer underlies a passivation layer over said channel region, said passivation layer comprising silicon oxynitride.
Claim 18
Dependent Claim
49 words
The method of claim 7 further comprising the following steps performed before the step of depositing said barrier layer: growing a tunnel oxide layer over said semiconductor substrate; forming floating gate members on said tunnel oxide layer; and forming a source region and a drain region within said substrate.
Claim 19
Dependent Claim
97 words
The method of claim 17, wherein said source region and said drain region define said channel region, wherein each floating gate member lies on said tunnel oxide layer over said channel region and at least a portion of said source and drain regions, wherein said tunnel oxide layer has a substantially uniform thickness between said floating gate member and said channel region, and wherein said barrier layer adequately overlies said source, said drain and said channel regions to block and/or getter hydrogen and said interconnecting layer makes electrical contact to said source region and/or said drain region.
Claim 20
Dependent Claim
24 words
The method of claim 18 wherein said barrier layer substantially overlies said channel region of each of said memory cells in said memory array.
Claim 21
Dependent Claim
23 words
The method of claim 19 wherein said barrier layer underlies a passivation layer over said channel region, said passivation layer comprising silicon oxynitride.
References Cited (Backward Citations)
GB284794A
Cited
US3879746A
Cited
US4121241A
Cited
US4288256A
Cited
US4267012A
Cited
US4375817A
Cited
WO1981000487A1
Cited
US4570328A
Cited
US4516145A
Cited
US4672740A
Cited
GB2156586A
Cited
US4845050A
Cited
US4566026A
Cited
US4743564A
Cited
US4870033A
Cited
US4931411A
Cited
US4804636A
Cited
US4807016A
Cited
EP0227549A2
Cited
US4707721A
Cited
JPS62276878A
Cited
EP0260232A2
Cited
US4782380A
Cited
US4824521A
Cited
US4814293A
Cited
GB2206234A
Cited
US4784973A
Cited
US4830974A
Cited
US4822753A
Cited
US4829024A
Cited
US4920073A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-19 | 1997-01-18 | 1997-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-19 | 2001-01-18 | 2001-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-19 | 2005-01-18 | 2005-07-20 | $7700.00 | Window Closed / Lapsed |