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Semiconductor device manufacturing method and semiconductor device manufactured thereby

Assignee: Toshiba Corp
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Filing: 1991-12-10
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Granted: 1993-05-18
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Expires: 2011-12-10
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Abstract

Abstract A method for manufacturing a semiconductor device comprises the steps of forming a polysilicon spacer on an after-oxide film on a semiconductor substrate, doping the polysilicon spacer by ion-implanting an impurity such as phosphorus, thermally diffusing the impurity into the polysilicon spacer, and eliminating the polysilicon spacer in part by etching. A semiconductor device manufactured by this method is also disclosed.

Inventors

  • 👤 Tatsuki Kizu
  • 👤 Shinichi Shimada
  • 👤 Kiyoshi Kobayashi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 22:33
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D64/00; H10D64/01; H10D64/021; H10P; H10P76/00; H10P76/40; H10P76/408; H10P76/4085

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 135 words
A method of manufacturing semiconductor devices comprising: forming a gate insulating film on the surface of a semiconductor substrate, within which substrate lightly doped impurity regions are formed; forming a gate electrode on said gate insulating film; forming an impurity polysilicon layer on said substrate over said gate electrode, the density of the impurity introduced in said polysilicon being sufficiently high to increase the etching speed of said polysilicon layer; selectively removing said impurity polysilicon layer by anisotropic etching in order to leave polysilicon spacers flanked on the side surface of said gate electrode; introducing an impurity into said impurity regions by the use of said gate electrode and said spacers as masks in order to form heavily doped impurity regions in said lightly doped impurity regions, respectively; and removing said spacers by selective etching.
Claim 2
Independent Claim 135 words
A method of manufacturing semiconductor devices comprising: forming a gate insulating film on the surface of a semiconductor substrate, within which substrate lightly doped impurity regions are formed; forming a gate electrode on said gate insulating film; forming an impurity polysilicon layer on said substrate over said gate electrode, the density of the impurity introduced in said polysilicon being sufficiently high to increase the etching speed of said polysilicon layer; selectively removing said impurity polysilicon layer by anisotropic etching in order to leave polysilicon spacers flanked on the side surface of said gate electrode; introducing an impurity into said impurity regions by the use of said gate electrode and said spacers as masks in order to form heavily doped impurity regions in said lightly doped impurity regions, respectively; and removing said spacers by selective etching.
Claim 3
Dependent Claim 21 words
The method of claim 1, wherein said impurity polysilicon layer is formed by the deposition of polysilicon followed by ion implantation.
Claim 4
Dependent Claim 20 words
The method of claim 2, wherein said impurity polysilicon layer is a polysilicon layer into which phosphorous has been introduced.
Claim 5
Dependent Claim 18 words
The method of claim 3, wherein said impurity polysilicon layer is thermally annealed after the introduction of phosphorous.
Claim 6
Dependent Claim 27 words
The method of claim 1 further comprising the step of forming a silicon oxide film on said gate electrode prior to the formation of said polysilicon layer.
Claim 7
Dependent Claim 24 words
The method of claim 5 wherein said silicon oxide film is formed as a dual film consisting of first and second silicon oxide films.
Claim 8
Dependent Claim 32 words
The method of claim 6 wherein said first silicon oxide film is formed by thermal treatment in a dry oxygen atmosphere whereas said second silicon oxide film is formed by BOX oxidation.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-05-17 1996-11-16 1997-05-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-05-17 2000-11-16 2001-05-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-05-17 2004-11-16 2005-05-18 $7700.00 Window Closed / Lapsed

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