US4784965A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Source drain doping technique
Assignee: Intel Corp
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Filing: 1987-09-16
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Granted: 1988-11-15
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Expires: 2007-09-16
Abstract
Abstract A method of forming metal oxide semiconductor field-effect transistors (MOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effect, to increase punch through voltage and to increase gate-aided breakdown voltage.
Inventors
- 👤 Been-Jon Woo
- 👤 Mark A. Holler
- 👤 Ender Hokeler
- 👤 Sandra S. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:12
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/0229; H10D30/60; H10D30/601; H10D30/605; H10D64/00; H10D64/01; H10D64/021; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0184; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/053; Y10S148/082; Y10S148/106
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
210 words
A method of fabricating a metal-oxide-semiconductor (MOS) integrated circuit where an insulated gate electrode member is formed on a portion of a semiconductor substrate, comprising the steps of: (a) forming an insulating layer over said substrate, including over opposite sides and upper surface of said gate member; (b) forming low temperature oxide spacer members on said opposite sides of said gate member over said insulating layer; (c) etching to remove upper surfaces of the structure resulting from step (b) wherein said spacers prevent etching of said insulating layer under said spacers until said spacers are completely removed causing said insulating layer to be thicker where said spacers prevented etching; (d) causing ions of a conductivity type determining impurity to impinge on the structure resulting from step (c) wherein ion implanted regions of said ions are formed in said substrate, said thicker insulating layer regions preventing a portion of said ions from reaching said substrate; (e) heating said substrate to diffuse at least a portion of said ions underneath said opposite sides of said gate member and to activate said ions such that said substrate adjacent to said gate member having lower concentration of ions than substrate disposed further from said gate member; whereby graded source and drain regions are formed.
Claim 2
Independent Claim
210 words
A method of fabricating a metal-oxide-semiconductor (MOS) integrated circuit where an insulated gate electrode member is formed on a portion of a semiconductor substrate, comprising the steps of: (a) forming an insulating layer over said substrate, including over opposite sides and upper surface of said gate member; (b) forming low temperature oxide spacer members on said opposite sides of said gate member over said insulating layer; (c) etching to remove upper surfaces of the structure resulting from step (b) wherein said spacers prevent etching of said insulating layer under said spacers until said spacers are completely removed causing said insulating layer to be thicker where said spacers prevented etching; (d) causing ions of a conductivity type determining impurity to impinge on the structure resulting from step (c) wherein ion implanted regions of said ions are formed in said substrate, said thicker insulating layer regions preventing a portion of said ions from reaching said substrate; (e) heating said substrate to diffuse at least a portion of said ions underneath said opposite sides of said gate member and to activate said ions such that said substrate adjacent to said gate member having lower concentration of ions than substrate disposed further from said gate member; whereby graded source and drain regions are formed.
Claim 3
Independent Claim
224 words
A method of fabricating a metal-oxide-semiconductor (MOS) integrated circuit where an insulated gate electrode member is formed on a portion of a semiconductor substrate, comprising the steps of: (a) forming a thermal oxidation insulating layer over said substrate, including over opposite sides and upper surface of said gate member; (b) forming low temperature oxide spacer members on said opposite sides of said gate member over said thermal oxidation insulating layer; (c) etching to remove upper surfaces of the structure resulting from step (b) wherein said spacers prevent etching of said thermal oxidation insulating layer under said spacers until said spacers are completely removed causing said thermal oxidation insulating layer to be thicker where said spacers prevented etching; (d) causing ions of a conductivity type determining impurity to impinge on the surface of the structure resulting from step (c) wherein ion implanted regions of said ions are formed in said substrate, said thicker insulating layer regions preventing a portion of said ions from reaching said substrate such that said substrate immediately adjacent to substrate underlying said gate member having lower concentration of ions than substrate disposed further from said gate member; (e) heating said substrate to diffuse at least a portion of said ions underneath said opposite sides of said gate member and to activate said ions, whereby graded source and drain regions are formed.
Claim 4
Independent Claim
224 words
A method of fabricating a metal-oxide-semiconductor (MOS) integrated circuit where an insulated gate electrode member is formed on a portion of a semiconductor substrate, comprising the steps of: (a) forming a thermal oxidation insulating layer over said substrate, including over opposite sides and upper surface of said gate member; (b) forming low temperature oxide spacer members on said opposite sides of said gate member over said thermal oxidation insulating layer; (c) etching to remove upper surfaces of the structure resulting from step (b) wherein said spacers prevent etching of said thermal oxidation insulating layer under said spacers until said spacers are completely removed causing said thermal oxidation insulating layer to be thicker where said spacers prevented etching; (d) causing ions of a conductivity type determining impurity to impinge on the surface of the structure resulting from step (c) wherein ion implanted regions of said ions are formed in said substrate, said thicker insulating layer regions preventing a portion of said ions from reaching said substrate such that said substrate immediately adjacent to substrate underlying said gate member having lower concentration of ions than substrate disposed further from said gate member; (e) heating said substrate to diffuse at least a portion of said ions underneath said opposite sides of said gate member and to activate said ions, whereby graded source and drain regions are formed.
Claim 5
Dependent Claim
49 words
The method of claim 2, further comprising the steps for forming said spacers of: (a) forming a low temperature oxide layer over said thermal oxidation insulating layer; and (b) selectively etching portions of said low temperature oxide layer to leave spacers on said opposite sides of said gate member.
Claim 6
Dependent Claim
70 words
The method of claim 2, further comprising the steps for forming said spacers of: (a) forming a low temperature oxide layer over said thermal oxidation insulating layer; (b) anisotropically etching said low temperature oxide layer; and (c) stopping said etching process after an appropriate time to remove only one thickness of said low temperature oxide layer, whereby low temperature oxide spacers remain on said opposite sides of said gate member.
Claim 7
Independent Claim
243 words
A method of fabricating a metal-oxide-semiconductor (MOS) integrated circuit comprising the steps of: (a) forming an insulated gate electrode member on a portion of the surface of a semiconductor substrate; (b) forming a thermal oxidation insulating layer over said substrate including over opposite sides and upper surface of said gate member; (c) forming a low temperature oxidation layer over said thermal oxidation insulating layer; (d) anisotropically etching said low temperature oxide layer; and, (e) stopping said etch process after an appropriate time to remove only one thickness of said low temperature oxide layer; (f) etching to remove upper surfaces of the structure resulting from step (e) wherein said spacers prevent etching of said thermal oxidation insulating layer under said spacers until said spacers are completely removed causing said thermal oxidation insulating layer to be thicker where said spacers prevented etching; (g) causing ions of a conductivity type determining impurity to impinge on the surface of the structure resulting from step (f) wherein ion implanted regions of said ions are formed in said substrate, said thicker insulating layer regions preventing a portion of said ions from reaching said substrate such that said substrate immediately adjacent to substrate underlying said gate member having lower concentration of ions than substrate disposed further from said gate member; (h) heating said substrate to diffuse at least a portion of said ions underneath said gate member and to activate said ions, whereby graded source and drain regions are formed.
Claim 8
Independent Claim
243 words
A method of fabricating a metal-oxide-semiconductor (MOS) integrated circuit comprising the steps of: (a) forming an insulated gate electrode member on a portion of the surface of a semiconductor substrate; (b) forming a thermal oxidation insulating layer over said substrate including over opposite sides and upper surface of said gate member; (c) forming a low temperature oxidation layer over said thermal oxidation insulating layer; (d) anisotropically etching said low temperature oxide layer; and, (e) stopping said etch process after an appropriate time to remove only one thickness of said low temperature oxide layer; (f) etching to remove upper surfaces of the structure resulting from step (e) wherein said spacers prevent etching of said thermal oxidation insulating layer under said spacers until said spacers are completely removed causing said thermal oxidation insulating layer to be thicker where said spacers prevented etching; (g) causing ions of a conductivity type determining impurity to impinge on the surface of the structure resulting from step (f) wherein ion implanted regions of said ions are formed in said substrate, said thicker insulating layer regions preventing a portion of said ions from reaching said substrate such that said substrate immediately adjacent to substrate underlying said gate member having lower concentration of ions than substrate disposed further from said gate member; (h) heating said substrate to diffuse at least a portion of said ions underneath said gate member and to activate said ions, whereby graded source and drain regions are formed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-15 | 1992-05-16 | 1992-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-15 | 1996-05-16 | 1996-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-15 | 2000-05-16 | 2000-11-15 | $7700.00 | Window Closed / Lapsed |