Shadow masking process for forming source and drain regions for field-effect transistors and like regions

Claim 2

An MOS process for forming source and drain regions in a substrate which includes a gate oxide layer and polysilicon layer comprising the steps of: defining a masking member on said polysilicon layer in a predetermined pattern; etching said polysilicon layer to form a gate employing said masking member as a mask, said etching being permitted to continue so as to undercut said masking member thereby forming overhangs which overhang said gate; ion implanting said substrate to form said source and drain regions through said gate oxide, the dosage level of ions implanted being selected so that a lower concentration of impurities is implanted in substrate regions beneath said overhangs than in substrate regions not protected by said masking member; whereby during subsequent processing steps, said lower concentration of impurities does not substantially diffuse, thereby providing more precise alignment between said gate and said source and drain regions.

Claim 3

The process defined by claim 1 wherein masking member is an oxide member.

Claim 4

The process defined by claim 2 wherein said ion implantation comprises arsenic implantation.

Claim 5

The process defined by claim 1 wherein said lower concentration of impurity is between 0.5% to 5% of the concentration level in said regions not protected by said masking member.

Claim 6

A process for forming an MOS field effect transistor on a substrate comprising the steps of: forming a gate oxide layer on said substrate; forming a layer of polysilicon over said gate oxide layer; defining a masking member on said polysilicon layer in a predetermined shape; etching said polysilicon layer employing said masking member as a mask to form a gate for said field-effect transistor, including etching said polysilicon layer under said masking member to form overhangs which overhang said gate and extend from said masking member; ion implanting said substrate to form source and drain regions by ion implanting through said gate oxide, such that some implantation occurs in the substrate region beneath said overhangs, thereby forming more lightly doped source and drain regions beneath said overhangs and more heavily doped source and drain regions in substrate areas unprotected by said masking member; whereby during subsequent processing steps, the lower concentration of impurities in said lightly doped source and drain regions does not substantially diffuse beneath said gate, thereby providing more precise alignment between said gate and said source and drain regions.

Claim 7

A process for forming an MOS field effect transistor on a substrate comprising the steps of: forming a gate oxide layer on said substrate; forming a layer of polysilicon over said gate oxide layer; defining a masking member on said polysilicon layer in a predetermined shape; etching said polysilicon layer employing said masking member as a mask to form a gate for said field-effect transistor, including etching said polysilicon layer under said masking member to form overhangs which overhang said gate and extend from said masking member; ion implanting said substrate to form source and drain regions by ion implanting through said gate oxide, such that some implantation occurs in the substrate region beneath said overhangs, thereby forming more lightly doped source and drain regions beneath said overhangs and more heavily doped source and drain regions in substrate areas unprotected by said masking member; whereby during subsequent processing steps, the lower concentration of impurities in said lightly doped source and drain regions does not substantially diffuse beneath said gate, thereby providing more precise alignment between said gate and said source and drain regions.

Claim 8

The process defined by claim 5 wheren said masking member is an oxide member.

Claim 9

The process defined by claim 6 wherein said ion implantation comprises arsenic implantation.

Claim 10

The process defined by claim 7 wherein said lower concentration of dopant in said more lightly doped source and drain regions is between 0.5% to 5% of the dopant concentration in said more heavily doped source and drain regions.

Claim 11

In a process for forming a doped region in a substrate which is in alignment with a circuit member, the improved steps comprising: forming a masking member on a layer, said masking member defining the outline of said circuit member; etching said layer employing said masking member as a mask to define said circuit member, said etching continuing such that said masking member overhangs said circuit member; ion implanting an inpurity into said substrate so as to form said doped region, the dosage level of ions implanted being selected such that ions are partially blocked by the overhang, thereby providing a more lightly doped region beneath said overhang which is an extension of said doped region; whereby in subsequent processing steps, said more lightly doped regions does not substantially diffuse beneath said circuit member.

Claim 12

In a process for forming a doped region in a substrate which is in alignment with a circuit member, the improved steps comprising: forming a masking member on a layer, said masking member defining the outline of said circuit member; etching said layer employing said masking member as a mask to define said circuit member, said etching continuing such that said masking member overhangs said circuit member; ion implanting an inpurity into said substrate so as to form said doped region, the dosage level of ions implanted being selected such that ions are partially blocked by the overhang, thereby providing a more lightly doped region beneath said overhang which is an extension of said doped region; whereby in subsequent processing steps, said more lightly doped regions does not substantially diffuse beneath said circuit member.