Method of forming an integrated circuit region through the combination of ion implantation and diffusion steps

Claim 1

In the fabrication of integrated circuits, a method of ion implantation into a semiconductor substrate comprising forming a bottom layer of an electrically insulative material on a surface of said substrate, forming an upper layer of another electrically insulative material on said bottom layer, said upper layer being an ion implantation barrier and more etchable than said bottom layer in selected solvents and said bottom layer being more etchable than said upper layer in selected solvents, etching at least one aperture through said upper layer to expose said bottom layer, etching at least one aperture through said bottom layer to expose said surface, said aperture being in registration with and having greater lateral dimensions than said aperture in said upper layer thereby undercutting the upper layer at the periphery of said opening, ion implanting conductivity-determining impurities of a selected type through said registered apertures into said substrate whereby said opening in said upper layer defines the lateral dimensions of said implantation and the portions of said substrate exposed by said undercutting at the periphery of said opening remain unimplanted, and diffusing a conductivity-determining impurity of said selected type through said registered apertures in said substrate whereby said diffusion is made into said unimplanted peripheral portions of said exposed substrate and extends laterally beyond said periphery of the opening in the bottom layer.