BICMOS process for forming shallow NPN emitters and mosfet source/drains

Claim 1

A device having a bipolar transistor and a field effect transistor, formed at a silicon surface of a substrate by a process comprising the steps of: forming in a first area of the surface a bipolar region, said bipolar region having an intrinsic base of the first conductivity type at said surface and a collector of a second conductivity type defining in a second area of the surface an MOS region of said second conductivity type; forming a polycrystalline silicon gate electrode in said MOS region and separated from the surface of the substrate by a gate oxide layer, source and drain regions being defined on either side of the gate electrode; exposing the source and drain regions; forming a layer of oxide in the first area over the intrinsic base region; forming an emitter opening and a base opening in said layer of oxide to expose the underlying surface at said intrinsic base region, said emitter opening and said base opening separated by a remaining portion of the oxide layer; forming a layer of refractory metal over the surface and contacting the exposed silicon surfaces; reacting the refractory metal to form a silicide film at the source and drain regions of the MOS region and at the base opening of the bipolar region; masking said emitter opening with a masking material; simultaneously implanting impurities of the first conductivity type into the silicide film formed at the source and drain regions of the MOS region and at the base opening; doping the surface of said intrinsic base at the location of said emitter opening with dopant of the second conductivity type; removing non-silicide portions of the refractory metal layer after the implanting step; and driving the impurities implanted into the silicide at said source and drain regions of said MOS region and at the base and emitter openings of said bipolar region downward therefrom to form p-n junctions therebelow.

Claim 2

A device having a bipolar transistor and a field effect transistor, formed at a silicon surface of a substrate by a process comprising the steps of: forming in a first area of the surface a bipolar region, said bipolar region having an intrinsic base of the first conductivity type at said surface and a collector of a second conductivity type defining in a second area of the surface an MOS region of said second conductivity type; forming a polycrystalline silicon gate electrode in said MOS region and separated from the surface of the substrate by a gate oxide layer, source and drain regions being defined on either side of the gate electrode; exposing the source and drain regions; forming a layer of oxide in the first area over the intrinsic base region; forming an emitter opening and a base opening in said layer of oxide to expose the underlying surface at said intrinsic base region, said emitter opening and said base opening separated by a remaining portion of the oxide layer; forming a layer of refractory metal over the surface and contacting the exposed silicon surfaces; reacting the refractory metal to form a silicide film at the source and drain regions of the MOS region and at the base opening of the bipolar region; masking said emitter opening with a masking material; simultaneously implanting impurities of the first conductivity type into the silicide film formed at the source and drain regions of the MOS region and at the base opening; doping the surface of said intrinsic base at the location of said emitter opening with dopant of the second conductivity type; removing non-silicide portions of the refractory metal layer after the implanting step; and driving the impurities implanted into the silicide at said source and drain regions of said MOS region and at the base and emitter openings of said bipolar region downward therefrom to form p-n junctions therebelow.

Claim 11

A device including a bipolar transistor and a field-effect transistor at a silicon surface of a substrate, formed by a process comprising: forming an n-type buried collector with a deep collector connection to said surface in a first area of the surface of said substrate; forming an intrinsic p-type base region overlying the buried collector; forming an n-type MOS region at the surface of the substrate isolated from the first area; forming a layer of gate oxide over the MOS region; forming a layer of polycrystalline silicon over the gate oxide layer; removing selected portions of the layer of polycrystalline silicon to form a gate electrode; forming an oxide layer over the intrinsic base region; exposing a source area and a drain area of said surface on opposite sides of said gate electrode in said MOS region, and exposing a base area in the base region, an emitter area in the base region to expose the surface of the silicon thereat, the base area separatred from the emitter area by a remaining portion of said oxide layer; forming a layer of titanium over the surface of the substrate and contacting the exposed surface of the silicon at the source, drain, base and emitter areas; reacting the portions of the layer of titanium contacting the exposed surface of the silicon at the source, drain base and emitter areas to form corresponding layers of titanium silicide thereat; masking off the silicide layers at the emitter area and simultaneously implanting p-type impurities into the silicide layers in the base area, and the source and drain areas in said MOS region; masking off the silicide layers in the MOS region and in the base area and implanting n-type impurities into the emitter area such that the n-type impurities are implanted into the silicide layer in the emitter area; after the implanting step, removing selected portions of the titanium layer not reacted to form silicide to form local interconnects with the remaining portions thereof; and driving the impurity materials to form p-n junctions beneath the silicide layers.

Claim 12

A device including a bipolar transistor and a field-effect transistor at a silicon surface of a substrate, formed by a process comprising: forming an n-type buried collector with a deep collector connection to said surface in a first area of the surface of said substrate; forming an intrinsic p-type base region overlying the buried collector; forming an n-type MOS region at the surface of the substrate isolated from the first area; forming a layer of gate oxide over the MOS region; forming a layer of polycrystalline silicon over the gate oxide layer; removing selected portions of the layer of polycrystalline silicon to form a gate electrode; forming an oxide layer over the intrinsic base region; exposing a source area and a drain area of said surface on opposite sides of said gate electrode in said MOS region, and exposing a base area in the base region, an emitter area in the base region to expose the surface of the silicon thereat, the base area separatred from the emitter area by a remaining portion of said oxide layer; forming a layer of titanium over the surface of the substrate and contacting the exposed surface of the silicon at the source, drain, base and emitter areas; reacting the portions of the layer of titanium contacting the exposed surface of the silicon at the source, drain base and emitter areas to form corresponding layers of titanium silicide thereat; masking off the silicide layers at the emitter area and simultaneously implanting p-type impurities into the silicide layers in the base area, and the source and drain areas in said MOS region; masking off the silicide layers in the MOS region and in the base area and implanting n-type impurities into the emitter area such that the n-type impurities are implanted into the silicide layer in the emitter area; after the implanting step, removing selected portions of the titanium layer not reacted to form silicide to form local interconnects with the remaining portions thereof; and driving the impurity materials to form p-n junctions beneath the silicide layers.