US3887993A
Expired / Lapsed
US
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Method of making an ohmic contact with a semiconductor substrate
Assignee: NEC Corp
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Filing: 1973-08-27
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Granted: 1975-06-10
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Expires: 1993-08-27
Abstract
Abstract Disclosed is a method of producing a semiconductor device in which a p-n junction and an ohmic contact with the semiconductor substrate are simultaneously formed. A layer of a metal containing an impurity of one conductivity type is deposited on a surface of a semiconductor body of the opposite conductivity type. The metal layer is then subjected to heat treatment, thereby to cause the impurity to diffuse into the semiconductor body to form the p-n junction. At the same time, a compound is formed of the metal and the semiconductor which serves as an ohmic contact with the semiconductor body at the region in which the impurity is diffused.
Inventors
- 👤 Takashi Okada
- 👤 Sokichi Yamagishi
- 👤 Mototaka Kamoshida
- 👤 Tomomitsu Satake
- 👤 Sadayuki Kishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 14:02
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/83; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/60; H10D64/62; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S148/00; Y10S148/043; Y10S148/106; Y10S148/147
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
216 words
A method of producing an insulatedgate field effect transistor comprising the steps of forming a gate insulator film on a predetermined surface region of a semiconductor substrate of one conductivity type, forming first, second and third layers of a metal, each of said metal layers containing an impurity of the opposite conductivity type on first and second surface regions of said semiconductor substrate and on said gate insulator film respectively, said first and second surface regions being adjacent to said predetermined surface region and being separated frOm each other, and subjecting said semiconductor substrate with said gate insulator film and said first, second and third layers of metal deposited thereon to heat treatment, to thereby diffuse said impurity contained in said first and second layers of metal into said first and second surface regions of said semiconductor substrate and form a compound of said metal and said semiconductor at said first and second surface regions, whereby said first surface region, said gate insulator film and said second surface region serve as the source region, gate insulator and drain region, respectively, of the field effect transistor and said compound of said metal and said semiconductor at said first and second surface regions serves as ohmic contacts to the source and drain regions of the field effect transistor.
Claim 2
Independent Claim
216 words
A method of producing an insulatedgate field effect transistor comprising the steps of forming a gate insulator film on a predetermined surface region of a semiconductor substrate of one conductivity type, forming first, second and third layers of a metal, each of said metal layers containing an impurity of the opposite conductivity type on first and second surface regions of said semiconductor substrate and on said gate insulator film respectively, said first and second surface regions being adjacent to said predetermined surface region and being separated frOm each other, and subjecting said semiconductor substrate with said gate insulator film and said first, second and third layers of metal deposited thereon to heat treatment, to thereby diffuse said impurity contained in said first and second layers of metal into said first and second surface regions of said semiconductor substrate and form a compound of said metal and said semiconductor at said first and second surface regions, whereby said first surface region, said gate insulator film and said second surface region serve as the source region, gate insulator and drain region, respectively, of the field effect transistor and said compound of said metal and said semiconductor at said first and second surface regions serves as ohmic contacts to the source and drain regions of the field effect transistor.
Claim 3
Dependent Claim
16 words
The method of claim 1, in which said metal is tungsten and said impurity is arsenic.
Claim 4
Dependent Claim
53 words
The method claimed in claim 1, wherein said metal is selected from a group consisting of tungsten, molybdenum, and platinum, and said impurity is selected from a group consisting of arsenic, boron, phosphorous and antimony, said impurity being contained in said metal in a concentration between 0.01 wt. % and 60 wt. %.
Claim 5
Independent Claim
318 words
A method of producing a semiconductor device having first and second insulated-gate field effect transistors, comprising the steps of forming a region of one conductivity type in a semiconductor substrate of the opposite conductivity type; forming first and second gate insulator films respectively on a first predetermined area in said one conductivity type region and a second predetermined area in said semiconductor substrate; depositing first, second, and third metal layers containing a first impurity of said opposite conductivity type respectively on a first surface region of said one conductivity type region, said first gate insulator film, and a second surface region of said one conductivity type region, said first and second surface regions being adjacent to said first gate insulator film and being separated from each other; depositing fourth, fifth, and sixth metal layers containing a second impurity of said one conductivity type on a third surface region of said substrate, said second gate insulator film, and a fourth surface region of said substrate, respectively, said third and fourth surface regions being adjacent to said second gate insulator film and being separated from each other; and subjecting said semiconductor substrate with said first and second gate insulator films and said first, second, third, fourth, fifth and sixth metal layers deposited thereon to heat treatment, to thereby diffuse said first impurity into said first and second surface regions and said second impurity into said third and fourth surface regions, whereby a first insulated-gate field effect transistor with said diffused first surface region, said first gate insulator film and said diffused second surface region serving as a source region, a gate insulator and a drain region, respectively, and a second insulated-gate field effect transistor with said diffused third surface region, said second gate insulator film and said diffused fourth surface region serving as a source region, a gate insulator and a drain region, respectively, are formed at the same time.
Claim 6
Independent Claim
318 words
A method of producing a semiconductor device having first and second insulated-gate field effect transistors, comprising the steps of forming a region of one conductivity type in a semiconductor substrate of the opposite conductivity type; forming first and second gate insulator films respectively on a first predetermined area in said one conductivity type region and a second predetermined area in said semiconductor substrate; depositing first, second, and third metal layers containing a first impurity of said opposite conductivity type respectively on a first surface region of said one conductivity type region, said first gate insulator film, and a second surface region of said one conductivity type region, said first and second surface regions being adjacent to said first gate insulator film and being separated from each other; depositing fourth, fifth, and sixth metal layers containing a second impurity of said one conductivity type on a third surface region of said substrate, said second gate insulator film, and a fourth surface region of said substrate, respectively, said third and fourth surface regions being adjacent to said second gate insulator film and being separated from each other; and subjecting said semiconductor substrate with said first and second gate insulator films and said first, second, third, fourth, fifth and sixth metal layers deposited thereon to heat treatment, to thereby diffuse said first impurity into said first and second surface regions and said second impurity into said third and fourth surface regions, whereby a first insulated-gate field effect transistor with said diffused first surface region, said first gate insulator film and said diffused second surface region serving as a source region, a gate insulator and a drain region, respectively, and a second insulated-gate field effect transistor with said diffused third surface region, said second gate insulator film and said diffused fourth surface region serving as a source region, a gate insulator and a drain region, respectively, are formed at the same time.
Claim 7
Dependent Claim
25 words
The method claimed in claim 4, wherein said metal layers are comprised of tungsten, said first impurity being arsenic and said second impurity being boron.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-09 | 1978-12-09 | 1979-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-09 | 1982-12-09 | 1983-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-09 | 1986-12-09 | 1987-06-10 | $7700.00 | Window Closed / Lapsed |