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US4705599A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for fabricating bipolar transistor in integrated circuit

Assignee: Mitsubishi Electric Corp
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Filing: 1986-08-26
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Granted: 1987-11-10
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Expires: 2006-08-26
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Abstract

Abstract In a method for fabricating a bipolar transistor in accordance with the present invention, a base electrode (9a) of metal silicide is formed being separated from an emitter region (7) only by the thickness of a double-layered insulator film (109, 203).

Inventors

  • 👤 Kakutaro Suda
  • 👤 Tadashi Hirao

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 10:06
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10D; H10D10/00; H10D10/01; H10D10/051; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10W20/064; H10W20/066

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 428 words
A method for fabricating a bipolar transistor, comprising the steps of: preparing a collector layer (3, 8) of a first conductivity type surrounded by an isolation oxide layer (102) on a semiconductor substrate; forming a multilayered film pattern by etching with a photoresist layer mask (303) thereon, said multilayered film including a polysilicon layer (600), a nitride layer (202) and an oxide layer (104) stacked in this order on said collector layer (3, 8); retracting said oxide layer (104) into between said nitride layer (202) and said photoresist layer (303) by side etching; selectively forming a first oxide film (105) on said collector layer (3, 8), utilizing said nitride layer (202) as a mask; etching down through said nitride layer (202) and said polysilicon layer (600) to a prescribed depth of said collector layer (3, 8) by anisotropic etching, utilizing both said side-etched oxide layer (104) and said first oxide film (105) as a mask; forming a second oxide film (106) on the etched and exposed surface area between said nitride layer region (202) and said first oxide film region (105); removing said nitride layer (202); introducing an impurity of said first conductivity type into said polysilicon layer (600), utilizing said second oxide film (106) as a mask; removing some of said second oxide film regions (106) to expose a regions in which a base layer and an emitter layer are going to be formed; implanting impurity ions into said exposed region to form a second conductivity type layer (5, 6) for implementing said base layer; implanting silicon ions into not only said exposed region but also predetermined regions of said first oxide film (105), said predetermined regions neighboring on said exposed region; subjecting said substrate to a heat treatment to complete said base layer (51, 61) by annealing said second conductivity type layer (5, 6) and simultaneously forming an emitter layer (7) by diffusion of said first conductivity type impurity from one (602) of said polysilicon layer regions; subjecting said substrate to an oxidation treatment at a relatively lower temperature to cover said exposed region with an oxide film (107, 108, 109), followed by formation of a nitride film (203) thereover to provide a double-layered insulator film; anisotropically etching said double-layered insulator film to leave it only on said side walls of both said emitter layer (7) and said polysilicon layer (603) thereon; and forming a base electrode (9a) and an emitter electrode (10a) on said silicon-implanted region, which are made of a metal silicide and insulated from each other by said double-layered insulator film (109, 203).
Claim 2
Independent Claim 428 words
A method for fabricating a bipolar transistor, comprising the steps of: preparing a collector layer (3, 8) of a first conductivity type surrounded by an isolation oxide layer (102) on a semiconductor substrate; forming a multilayered film pattern by etching with a photoresist layer mask (303) thereon, said multilayered film including a polysilicon layer (600), a nitride layer (202) and an oxide layer (104) stacked in this order on said collector layer (3, 8); retracting said oxide layer (104) into between said nitride layer (202) and said photoresist layer (303) by side etching; selectively forming a first oxide film (105) on said collector layer (3, 8), utilizing said nitride layer (202) as a mask; etching down through said nitride layer (202) and said polysilicon layer (600) to a prescribed depth of said collector layer (3, 8) by anisotropic etching, utilizing both said side-etched oxide layer (104) and said first oxide film (105) as a mask; forming a second oxide film (106) on the etched and exposed surface area between said nitride layer region (202) and said first oxide film region (105); removing said nitride layer (202); introducing an impurity of said first conductivity type into said polysilicon layer (600), utilizing said second oxide film (106) as a mask; removing some of said second oxide film regions (106) to expose a regions in which a base layer and an emitter layer are going to be formed; implanting impurity ions into said exposed region to form a second conductivity type layer (5, 6) for implementing said base layer; implanting silicon ions into not only said exposed region but also predetermined regions of said first oxide film (105), said predetermined regions neighboring on said exposed region; subjecting said substrate to a heat treatment to complete said base layer (51, 61) by annealing said second conductivity type layer (5, 6) and simultaneously forming an emitter layer (7) by diffusion of said first conductivity type impurity from one (602) of said polysilicon layer regions; subjecting said substrate to an oxidation treatment at a relatively lower temperature to cover said exposed region with an oxide film (107, 108, 109), followed by formation of a nitride film (203) thereover to provide a double-layered insulator film; anisotropically etching said double-layered insulator film to leave it only on said side walls of both said emitter layer (7) and said polysilicon layer (603) thereon; and forming a base electrode (9a) and an emitter electrode (10a) on said silicon-implanted region, which are made of a metal silicide and insulated from each other by said double-layered insulator film (109, 203).
Claim 3
Dependent Claim 39 words
The method in accordance with claim 1, wherein said prescribed depth in the fifth step is such as to enable the base-emitter interface to be level with the interface of said base layer (51) and said base electrode (9a).

References Cited (Backward Citations)

US4445268A Cited
US4486942A Cited
US4484388A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-11-09 1991-05-11 1991-11-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-11-09 1995-05-11 1995-11-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-11-09 1999-05-11 1999-11-10 $7700.00 Window Closed / Lapsed

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