US6895136B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated optical/electronic circuits and associated methods of simultaneous generation thereof
Assignee: Cisco Technology Inc
•
Filing: 2004-07-13
•
Granted: 2005-05-17
•
Expires: 2024-07-13
Abstract
Abstract A method for forming a hybrid active electronic and optical circuit using a lithography mask. The hybrid active electronic and optical circuit comprising an active electronic device and at least one optical device on a Silicon-On-Insulator (SOI) wafer. The SOI wafer including an insulator layer and an upper silicon layer. The upper silicon layer including at least one component of the active electronic device and at least one component of the optical device. The method comprising projecting the lithography mask onto the SOI waver in order to simultaneously pattern the component of the active electronic device and the component of the optical device on the SOI wafer.
Inventors
- 👤 Shrenik Deliwala
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 02:22
CPC Classifications
G; G02; G02B; G02B6/00; G02B6/10; G02B6/12; G02B6/12007; G02B6/12009; G02B6/12033; B; B82; B82Y; B82Y20/00; G02B27/00; G02B27/28; G02B27/283; G02B27/285; G02B5/00; G02B5/04; G02B5/045; G02B6/12004; G02B6/12011; G02B6/12026; G02B6/122; G02B6/1225; G02B6/1228; G02B6/124; G02B6/24; G02B6/26; G02B6/28; G02B6/2804; G02B6/2861; G02F; G02F1/00; G02F1/01; G02F1/015; G02F1/025; G02F1/29; G02F1/295; H; H10; H10D; H10D86/00; H10D86/201; G02B2006/12035; G02B2006/12038; G02B2006/12061; G02B2006/12083; G02B2006/12097; G02B2006/12104; G02B2006/12107; G02B2006/12114; G02B2006/12133; G02B2006/12135; G02B2006/12161; G02B2006/12164; G02B2006/12166; G02B2006/12176; G02B6/293; G02B6/29346; G02B6/29349; G02B6/29358; G02B6/34; G02B6/42; G02B6/4201; G02B6/4204; G02B6/4215; G02B6/4219; G02B6/4228; G02B6/4232; G02B6/43; G02F1/0147; G02F1/0151; G02F1/0152; G02F2201/00; G02F2201/20
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
163 words
A method for forming a hybrid active electronic and optical circuit using a lithography mask, the hybrid active electronic and optical circuit comprising an active electronic device and at least one active optical device, both devices disposed at least in part in a single Silicon-On-Insulator (SOI) wafer, the SOI wafer including an insulator layer and an upper silicon layer, the upper silicon layer including at least one component of the active electronic and at least one component of the active optical device, the active optical device also comprising a polysilicon region disposed above the upper silicon layer forming a polysilicon loaded region wherein the higher effective mode index of the polysilicon loaded region controls the confinement of the light propagating within the upper silicon layer, the method comprising projecting the lithography mask onto the SOI wafer in order to simultaneously pattern at least a portion of the active electronic device and at least a portion of the at least one active optical device.
Claim 2
Independent Claim
163 words
A method for forming a hybrid active electronic and optical circuit using a lithography mask, the hybrid active electronic and optical circuit comprising an active electronic device and at least one active optical device, both devices disposed at least in part in a single Silicon-On-Insulator (SOI) wafer, the SOI wafer including an insulator layer and an upper silicon layer, the upper silicon layer including at least one component of the active electronic and at least one component of the active optical device, the active optical device also comprising a polysilicon region disposed above the upper silicon layer forming a polysilicon loaded region wherein the higher effective mode index of the polysilicon loaded region controls the confinement of the light propagating within the upper silicon layer, the method comprising projecting the lithography mask onto the SOI wafer in order to simultaneously pattern at least a portion of the active electronic device and at least a portion of the at least one active optical device.
Claim 3
Dependent Claim
35 words
The method as defined in claim 1 wherein the active optical device includes one from the group of a p-n device, a field plated device, a Schottky device, a MOSCAP device and a MOSFET device.
Claim 4
Dependent Claim
87 words
The method as defined in claim 2 wherein the active optical device is a MOSCAP device and further includes a relatively thin oxide layer disposed between the upper silicon layer and the polysilicon region such that the MOSCAP device is defined by the upper silicon layer of the SOI wafer forming the “Semiconductor” portion of the MOSCAP device, the relatively thin oxide layer forming the “Oxide” portion of the MOSCAP device and the polysilicon region is sufficiently doped to form the “Metal” portion of the MOSCAP device.
Claim 5
Dependent Claim
87 words
The method as defined in claim 2 wherein the active optical device is a MOSFET device and further includes a relatively thin oxide layer disposed between the upper silicon layer and the polysilicon region such that the MOSFET device is defined by the upper silicon layer of the SOI wafer forming the “Semiconductor” portion of the MOSFET device, the relatively thin oxide layer forming the “Oxide” portion of the MOSFET device and the polysilicon region is sufficiently doped to form the “Metal” portion of the MOSFET device.
Claim 6
Dependent Claim
36 words
The method as defined in claim 1 wherein the polysilicon region is positioned and shaped to create a desired position and shape of the optical mode field within the upper silicon layer and the polysilicon region.
Claim 7
Dependent Claim
22 words
The method as defined in claim 1 wherein the polysilicon region comprises multiple layers of polysilicon disposed above the upper silicon layer.
Claim 8
Dependent Claim
40 words
The method as defined in claim 6 wherein the multiple layer polysilicon region is positioned and shaped to create a desired position and shape of the optical mode field within the upper silicon layer and the multiple layer polysilicon region.
Claim 9
Dependent Claim
35 words
The method as defined in claim 6 wherein the active optical device includes one from the group of a p-n device, a field plated device, a Schottky device, a MOSCAP device and a MOSFET device.
Claim 10
Dependent Claim
96 words
The method as defined in claim 8 wherein the active optical device is a MOSCAP device and further includes a relatively thin oxide layer disposed between the upper silicon layer and the multiple layer polysilicon region such that the MOSCAP device is defined by the upper silicon layer of the SOI wafer forming the “Semiconductor” portion of the MOSCAP device, the relatively thin oxide layer forming the “Oxide” portion of the MOSCAP device and at least one layer of the multiple layer polysilicon region is sufficiently doped to form the “Metal” portion of the MOSCAP device.
Claim 11
Dependent Claim
97 words
The method as defined in claim 8 wherein the active optical device is a MOSCAP device and further includes a relatively thin oxide layer disposed between the upper silicon layer and the multiple layer polysilicon region such that the MOSCAP device is defined by the upper silicon layer of the SOI wafer forming the “Semiconductor” portion of the MOSCAP device, the relatively thin oxide layer forming the “Oxide” portion of the MOSCAP device and at least one layer of the multiple layer polysilicon region is lightly doped to form a semiconductor layer of the active optical device.
Claim 12
Dependent Claim
176 words
A hybrid electronic and optical circuit integrated with a Silicon-On-Insulator (SOI) wafer, the SOI wafer including an insulator layer and an upper silicon layer, the hybrid active electronic and optical circuit comprising: a relatively thin optical waveguide formed within at least a portion of the upper silicon layer of the SOI wafer; and at least one active optical device including both a portion of the relatively thin optical waveguide within the upper silicon layer of the SOI wafer and a polysilicon region disposed above the upper silicon layer so as to form a polysilicon loaded region wherein the higher effective mode index of the polysilicon loaded region controls the confinement of the light propagating within the upper silicon layer and wherein altering an electric voltage applied between the polysilicon region and the upper silicon layer affects a free carrier distribution in a portion of the at least one active optical device, thereby changing the effective mode index of the at least one active optical device and altering the optical characteristics of a lightwave signal passing therethrough.
Claim 13
Dependent Claim
176 words
A hybrid electronic and optical circuit integrated with a Silicon-On-Insulator (SOI) wafer, the SOI wafer including an insulator layer and an upper silicon layer, the hybrid active electronic and optical circuit comprising: a relatively thin optical waveguide formed within at least a portion of the upper silicon layer of the SOI wafer; and at least one active optical device including both a portion of the relatively thin optical waveguide within the upper silicon layer of the SOI wafer and a polysilicon region disposed above the upper silicon layer so as to form a polysilicon loaded region wherein the higher effective mode index of the polysilicon loaded region controls the confinement of the light propagating within the upper silicon layer and wherein altering an electric voltage applied between the polysilicon region and the upper silicon layer affects a free carrier distribution in a portion of the at least one active optical device, thereby changing the effective mode index of the at least one active optical device and altering the optical characteristics of a lightwave signal passing therethrough.
Claim 14
Dependent Claim
40 words
The hybrid active electronic and optical circuit as defined in claim 11 wherein the active optical device includes one from the group of a p-n device, a field plated device, a Schottky device, a MOSCAP device and a MOSFET device.
Claim 15
Dependent Claim
115 words
The hybrid active electronic and optical circuit as defined in claim 12 wherein the active optical device further includes a relatively thin oxide layer disposed between the upper silicon layer and the polysilicon region such that the MOSCAP device structure is defined by the upper silicon layer of the SOI wafer forming the “Semiconductor” portion of the MOSCAP device, the relatively thin oxide layer forming the “Oxide” portion of the MOSCAP device and the polysilicon region is sufficiently doped to form the “Metal” portion of the MOSCAP device wherein the altering of an electric voltage applied between the polysilicon region and the upper silicon layer affects the distribution of free carriers near the semiconductor/oxide boundary.
Claim 16
Dependent Claim
41 words
The hybrid active electronic and optical circuit as defined in claim 11 wherein the polysilicon region is positioned and shaped to create the desired position and shape of the optical mode field within the upper silicon layer and the polysilicon region.
Claim 17
Dependent Claim
27 words
The hybrid active electronic and optical circuit as defined in claim 11 wherein the polysilicon region comprises multiple layers of polysilicon disposed above the upper silicon layer.
Claim 18
Dependent Claim
45 words
The hybrid active electronic and optical circuit as defined in claim 15 wherein the multiple layer polysilicon region is positioned and shaped to create a desired position and shape of the optical mode field within the upper silicon layer and the multiple layer polysilicon region.
Claim 19
Dependent Claim
40 words
The hybrid active electronic and optical circuit as defined in claim 15 wherein the active optical device includes one from the group of a p-n device, a field plated device, a Schottky device, a MOSCAP device and a MOSFET device.
Claim 20
Dependent Claim
128 words
The hybrid active electronic and optical circuit as defined in claim 17 wherein the active optical device is a MOSCAP device and further includes a relatively thin oxide layer disposed between the upper silicon layer and the multiple layer polysilicon region such that the MOSCAP device is defined by the upper silicon layer of the SOI wafer forming the “Semiconductor” portion of the MOSCAP device, the relatively thin oxide layer forming the “Oxide” portion of the MOSCAP device and at least one layer of the multiple layer polysilicon region is sufficiently doped to form the “Metal” portion of the MOSCAP device wherein the altering of an electric voltage applied between the polysilicon region and the upper silicon layer affects the distribution of free carriers near the semiconductor/oxide boundary.
Claim 21
Dependent Claim
129 words
The hybrid active electronic and optical circuit as defined in claim 17 wherein the active optical device is a MOSCAP device and further includes a relatively thin oxide layer disposed between the upper silicon layer and the multiple layer polysilicon region such that the MOSCAP device is defined by the upper silicon layer of the SOI wafer forming the “Semiconductor” portion of the MOSCAP device, the relatively thin oxide layer forming the “Oxide” portion of the MOSCAP device and at least one layer of the multiple layer polysilicon region is lightly doped to form a semiconductor layer of the active optical device wherein the altering of an electric voltage applied between the polysilicon region and the upper silicon layer affects the distribution of free carriers near the semiconductor/oxide boundaries.
Claim 22
Dependent Claim
92 words
The hybrid active electronic and optical circuit as defined in claim 17 wherein the active optical device is a MOSFET device and further includes a relatively thin oxide layer disposed between the upper silicon layer and the polysilicon region such that the MOSFET device is defined by the upper silicon layer of the SOI wafer forming the “Semiconductor” portion of the MOSFET device, the relatively thin oxide layer forming the “Oxide” portion of the MOSFET device and the polysilicon region is sufficiently doped to form the “Metal” portion of the MOSFET device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-05-16 | 2008-11-15 | 2009-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-05-16 | 2012-11-15 | 2013-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-05-16 | 2016-11-15 | 2017-05-17 | $7700.00 | Window Closed / Lapsed |