US6316281B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating a hybrid optical integrated circuit employing SOI optical waveguide
Assignee: Uniloc 2017 LLC
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Filing: 1999-09-10
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Granted: 2001-11-13
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Expires: 2019-09-10
Abstract
Abstract The present invention relates to an optical integrated circuit; and, more particularly, to a method for preparing an improved hybrid optical integrated circuit which is capable of accommodating optical waveguides, optical devices, such as light emitting devices and light receiving devices, and optical fibers in an effective manner. The present invention has the advantages of minimizing horizontal misalignment error between the SOI waveguide rib area, the V-groove etch window and the alignment marks, decreasing the manufacturing cost by passively aligning the waveguides, the optical devices and the optical fibers on a single substrate. Also, the present invention has an effect of reducing fresnel reflection loss by providing the LPCVD silicon nitride layer capable of being used as an anti-reflection coating layer at both ends of the waveguide.
Inventors
- 👤 Sang Hwan Lee
- 👤 Gwan Chong Joo
- 👤 Nam Hwang
- 👤 Min Kyu Song
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 03:53
CPC Classifications
G; G02; G02B; G02B6/00; G02B6/24; G02B6/42; G02B6/4201; G02B6/4219; G02B6/4228; G02B6/423; H; H10; H10F; H10F99/00; G02B6/10; G02B6/12; G02B6/13; G02B6/136; G02B6/4236; G02B6/424; G02B6/4243; H10D; H10D86/00; H10F77/00; H10F77/40; H10F77/407; G02B6/26; G02B6/30; G02B6/4204; G02B6/4214; G02B6/422; G02B6/4221; G02B6/4224; G02B6/4232
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
236 words
A method for fabricating a hybrid optical integrated circuit, the method comprising the steps of: a) providing a SOI wafer including a silicon substrate, a buried insulating layer and a single crystal silicon layer; b) selectively etching the single crystal silicon layer, thereby forming a SOI slab; c) forming a silicon nitride layer and an etching mask layer on the resulting structure, wherein the silicon nitride layer is formed by a low pressure chemical vapor deposition process; d) selectively etching the etching mask layer and the silicon nitride layer to expose the single crystal silicon layer in the SOI slab except a rib area and simultaneously forming a V-groove etch window for aligning an optical fiber and marks for aligning an optical device, wherein the a rib region in the SOI slab is covered with the silicon nitride layer and the etching mask layer; e) selectively etching the exposed single crystal silicon layer to form a SOI rib; f) selectively etching the etching mask layer and the silicon nitride layer on the SOI rib; g) forming a cladding layer for an optical waveguide on a surface of the SOI slab and the SOI rib; h) anisotropically etching the silicon substrate exposed through the V-groove etch window to form an optical fiber guiding V-groove; and i) selectively removing the etching mask layer positioned at both end facets of the SOI slab and exposing the silicon nitride layer.
Claim 2
Independent Claim
236 words
A method for fabricating a hybrid optical integrated circuit, the method comprising the steps of: a) providing a SOI wafer including a silicon substrate, a buried insulating layer and a single crystal silicon layer; b) selectively etching the single crystal silicon layer, thereby forming a SOI slab; c) forming a silicon nitride layer and an etching mask layer on the resulting structure, wherein the silicon nitride layer is formed by a low pressure chemical vapor deposition process; d) selectively etching the etching mask layer and the silicon nitride layer to expose the single crystal silicon layer in the SOI slab except a rib area and simultaneously forming a V-groove etch window for aligning an optical fiber and marks for aligning an optical device, wherein the a rib region in the SOI slab is covered with the silicon nitride layer and the etching mask layer; e) selectively etching the exposed single crystal silicon layer to form a SOI rib; f) selectively etching the etching mask layer and the silicon nitride layer on the SOI rib; g) forming a cladding layer for an optical waveguide on a surface of the SOI slab and the SOI rib; h) anisotropically etching the silicon substrate exposed through the V-groove etch window to form an optical fiber guiding V-groove; and i) selectively removing the etching mask layer positioned at both end facets of the SOI slab and exposing the silicon nitride layer.
Claim 3
Dependent Claim
31 words
The method in accordance with claim 1 , wherein the method further comprises the step of forming a trench crossing the optical fiber guiding V-groove, being adjacent to the SOI slab.
Claim 4
Dependent Claim
38 words
The method in accordance with claim 1 , wherein the step g) further comprises the step of forming a metal pad for electrically connecting the optical device to the SOI wafer and a metal pad for solder bumps.
Claim 5
Dependent Claim
20 words
The method in accordance with claim 3 , wherein the method further comprises the step of forming the solder bumps.
Claim 6
Dependent Claim
17 words
The method in accordance with claim 1 , wherein the SOI slab is in a Y-branch type.
Claim 7
Dependent Claim
14 words
The method in accordance with claim 1 , wherein the SOI rib is tapered.
Claim 8
Dependent Claim
43 words
The method in accordance with claim 1 , wherein the silicon nitride layer is formed by a LPCVD (low pressure chemical vapor deposition) method and a thickness (t) of the silicon nitride layer is given by: t=nλ/ 4 (λ: wavelength and n: integer)
Claim 9
Dependent Claim
24 words
The method in accordance with claim 1 , wherein the cladding layer is a silicon oxide layer which is formed by a thermal oxidation.
Claim 10
Dependent Claim
58 words
The method in accordance with claim 1 , wherein a ratio of a height of the SOI rib to a thickness of the single crystal silicon layer and a ratio of the height of the SOI rib to a width of the SOI rib are controlled to transmit only one fundamental mode in a vertical and horizontal direction.
Claim 11
Dependent Claim
18 words
The method in accordance with claim 1 , wherein the single crystal silicon layer has a <100> direction.
Claim 12
Dependent Claim
38 words
The method in accordance with claim 10 , wherein the SOI rib and the V-groove etch window are aligned in the <110> direction so that the V-groove etch window is surrounded with a surface of (111) crystalline plane.
References Cited (Backward Citations)
US4639074A
Cited
US4735677A
Cited
US4877299A
Cited
US5757986A
Cited
US5641612A
Cited
US5787214A
Cited
US5703973A
Cited
US5881190A
Cited
US5854867A
Cited
US6058234A
Cited
US6108478A
Cited
US6157759A
Cited
US6163632A
Cited
US6217232B1
Cited
US6101210A
Cited
US6063299A
Cited
US6231771B1
Cited
US6222951B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-11-12 | 2005-05-14 | 2005-11-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-11-12 | 2009-05-14 | 2009-11-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-11-12 | 2013-05-14 | 2013-11-13 | $7700.00 | Window Closed / Lapsed |