US5233218A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor wafer and process for producing same
Assignee: Fujitsu Ltd
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Filing: 1991-09-19
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Granted: 1993-08-03
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Expires: 2011-09-19
Abstract
Abstract A silicon-on-insulator type semiconductor wafer comprising: an upper silicon semiconductor layer used for forming electronic elements thereon; a lower silicon semiconductor layer acting as a support for the entire wafer; an intermediate silicon oxide layer inserted between the upper and lower portions and acting as an insulating layer, and a circumferential portion for protecting the silicon oxide layer, at least at the periphery thereof, against an agent for dissolving silicon oxide.
Inventors
- 👤 Takao Miura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:35
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10W; H10W10/00; H10W10/10; H10W10/181
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
101 words
A silicon-on-insulator type semiconductor wafer comprising: an upper semiconductor layer of single crystalline silicon used for forming electronic elements thereon; a lower semiconductor layer of single crystalline silicon acting as a support for the entire wafer; an intermediate silicon oxide layer inserted between said upper and lower layers and acting as an insulating layer; and a circumferential layer having a smooth curved surface of protecting said intermediate silicon oxide layer at the periphery thereof against an agent for dissolving silicon oxide, wherein provision of the circumferential layer and the upper semiconductor layer prevents said intermediate silicon oxide layer from being exposed.
Claim 2
Dependent Claim
101 words
A silicon-on-insulator type semiconductor wafer comprising: an upper semiconductor layer of single crystalline silicon used for forming electronic elements thereon; a lower semiconductor layer of single crystalline silicon acting as a support for the entire wafer; an intermediate silicon oxide layer inserted between said upper and lower layers and acting as an insulating layer; and a circumferential layer having a smooth curved surface of protecting said intermediate silicon oxide layer at the periphery thereof against an agent for dissolving silicon oxide, wherein provision of the circumferential layer and the upper semiconductor layer prevents said intermediate silicon oxide layer from being exposed.
Claim 3
Dependent Claim
35 words
A semiconductor wafer according to claim 1, wherein said silicon-on-insulator wafer is produced by a lamination method, in which an all-silicon wafer is laminated on a silicon wafer having a silicon oxide layer formed thereon.
Claim 4
Dependent Claim
37 words
A semiconductor wafer according to claim 1, wherein said silicon-on-insulator type wafer is produced by a separation-by-implanted-oxygen (SIMOX) method, in which oxygen ions are implanted into a silicon wafer to form an insulating layer of silicon oxide.
Claim 5
Dependent Claim
18 words
A semiconductor wafer according to claim 1, wherein said circumferential layer is composed of a fluoric acid-resisting substance.
Claim 6
Dependent Claim
37 words
A semiconductor wafer according to claim 4, wherein said circumferential layer is composed of one or more layers of at least one selected from the group consisting of Si, Si 3 N 4 , SiC, and SiGe.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-02 | 1997-02-01 | 1997-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-02 | 2001-02-01 | 2001-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-02 | 2005-02-01 | 2005-08-03 | $7700.00 | Window Closed / Lapsed |