Patent US6593176B2 successfully refreshed from Google Patents.
US6593176B2
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US
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Method for forming phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact
Assignee: Ovonyx Memory Technology LLC
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Filing: 2002-07-15
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Granted: 2003-07-15
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Expires: 2022-07-15
Abstract
Abstract The invention relates to a process of forming a phase-change memory device. The process includes forming a salicide structure in peripheral logic portion of the substrate and preventing forming salicide structures in the memory array. The device may include a double-wide trench into which a single film is deposited but two isolated lower electrodes are formed therefrom. Additionally a diode stack is formed that communicates to the lower electrode.
Inventors
- 👤 Charles Dennison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 10:43
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/30; H10D48/32; H10D48/366; H10B; H10B63/00; H10B63/20; H10B63/80; H10N; H10N70/00; H10N70/011; H10N70/20; H10N70/231; H10N70/801; H10N70/821; H10N70/826; H10N70/841; H10N70/8413; H10N70/881; H10N70/882; H10N70/8828
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
80 words
In a memory array, a process of forming a phase-change memory cell comprising: forming an isolation structure; forming an N+ base below the isolation structure; forming a protective layer over the memory array; selectively removing the protective layer to form a silicided CMOS device in a region peripheral to the memory array; forming a lower electrode in a first recess, wherein the lower electrode touches a self-aligned emitter active area below the first recess; and forming a phase-change memory element.
Claim 2
Dependent Claim
80 words
In a memory array, a process of forming a phase-change memory cell comprising: forming an isolation structure; forming an N+ base below the isolation structure; forming a protective layer over the memory array; selectively removing the protective layer to form a silicided CMOS device in a region peripheral to the memory array; forming a lower electrode in a first recess, wherein the lower electrode touches a self-aligned emitter active area below the first recess; and forming a phase-change memory element.
Claim 3
Dependent Claim
29 words
The process according to claim 1 , further comprising: forming a contact in a second recess, wherein the contact touches a self-aligned base active area below the second recess.
Claim 4
Dependent Claim
71 words
The process according to claim 1 , wherein forming a CMOS device comprises: patterning a first mask over the memory array and over a first portion of the peripheral region; implanting a second portion of the periphery to form an NMOS device; patterning a second mask over the memory array and over the second portion of the periphery; and implanting the first portion of the periphery to form a PMOS device.
Claim 5
Dependent Claim
116 words
The process according to claim 1 , wherein forming a CMOS device comprises: patterning a first mask over the memory array and over a first portion of the peripheral region; removing the protective layer that is exposed by the first mask and that comprises a second portion of the peripheral region; implanting the second portion of the peripheral region to form an NMOS device; patterning a second mask over the memory array and over the second portion of the peripheral region; removing the protective layer that is exposed by the second mask and that comprises the first portion of the peripheral region; and implanting the first portion of the peripheral region to form a PMOS device.
Claim 6
Dependent Claim
29 words
The process according to claim 1 , wherein forming CMOS device comprises: forming self-aligned silicide structures under conditions that resist formation of self-aligned silicide structures in the memory array.
Claim 7
Dependent Claim
30 words
The process according to claim 1 , wherein forming a CMOS device comprises: removing the protective layer from the peripheral region; and forming self-aligned silicide structures in the peripheral region.
Claim 8
Dependent Claim
46 words
The process according to claim 1 , further comprising: forming a masking material over the memory array; forming a dielectric material over the masking material; etching the dielectric material to stop on the masking material; and etching the masking material to stop on the memory array.
Claim 9
Dependent Claim
39 words
The process according to claim 1 , further comprising: forming a masking material over the memory array; forming a dielectric material over the masking material; etching the dielectric material and the masking material to stop on the memory array.
Claim 10
Dependent Claim
48 words
The process according to claim 1 , following forming a protective layer, further comprising: forming a masking material over the memory array and over the peripheral region; patterning the masking material over the memory array; and etching through the masking material to further define the emitter active area.
Claim 11
Dependent Claim
48 words
The process according to claim 1 , wherein forming a lower electrode comprises: forming a polysilicon film in the first recess; doping a portion of the polysilicon film including a portion that makes contact with the self-aligned emitter active area; and activating the doping in the polysilicon film.
Claim 12
Dependent Claim
83 words
The process according to claim 1 , wherein forming a lower electrode comprises: forming a polysilicon film in the first recess; doping a portion of the polysilicon film including a portion that makes contact with the self-aligned emitter active area, under conditions to form a first undoped portion and a second doped portion; modifying a portion of the second doped portion to achieve a lower conductivity in the modified portion than the second doped portion; and activating the doping in the polysilicon film.
Claim 13
Dependent Claim
61 words
The process according to claim 2 , wherein forming a contact in a second recess further comprises: etching a via in at least one dielectric material to expose a contact surface in a substrate; implanting N-type dopant into the contact surface to form an N-type base; forming a barrier material in the via; and filling the via with a conductive material.
Claim 14
Dependent Claim
116 words
The process according to claim 1 , wherein forming a lower electrode comprises: forming the first recess under conditions that expose two active areas in a first direction and at least two active areas in a second direction that is orthogonal to the first direction; forming a polysilicon film in the first recess; doping a portion of the polysilicon film in a first direction to achieve a first conductivity at the bottom of the first recess and a second conductivity in the first direction; and doping a portion of the polysilicon film in a second direction to maintain the first conductivity at the bottom of the first recess and the second conductivity in the second direction.
Claim 15
Dependent Claim
20 words
The process according to claim 1 , further comprising: singulating the lower electrode to form a plurality of lower electrodes.
Claim 16
Dependent Claim
131 words
A process of forming a memory cell comprising: forming a first shallow isolation trench in a memory array; forming an N+ base implantation in the memory array; forming a protective layer over the memory array; forming a CMOS device in a peripheral region; forming a first dielectric layer over the memory array; forming a first recess in the first dielectric layer; forming a self-aligned emitter active area below the first recess; forming a lower electrode in the first recess; forming a phase-change element in contact with the lower electrode; forming a top electrode in contact with the phase-change element; forming a second dielectric layer over the top electrode; forming a contact hole in the second dielectric layer; and forming a self-aligned base active area at the bottom of the contact hole.
Claim 17
Dependent Claim
131 words
A process of forming a memory cell comprising: forming a first shallow isolation trench in a memory array; forming an N+ base implantation in the memory array; forming a protective layer over the memory array; forming a CMOS device in a peripheral region; forming a first dielectric layer over the memory array; forming a first recess in the first dielectric layer; forming a self-aligned emitter active area below the first recess; forming a lower electrode in the first recess; forming a phase-change element in contact with the lower electrode; forming a top electrode in contact with the phase-change element; forming a second dielectric layer over the top electrode; forming a contact hole in the second dielectric layer; and forming a self-aligned base active area at the bottom of the contact hole.
Claim 18
Dependent Claim
74 words
The process according to claim 15 , wherein forming a CMOS device comprises: patterning a first mask over the memory array and over a first portion of the peripheral region; implanting a second portion of the peripheral region to form an NMOS device; patterning a second mask over the memory array and over the second portion of the peripheral region; and implanting the first portion of the peripheral region to form a PMOS device.
Claim 19
Dependent Claim
116 words
The process according to claim 15 , wherein forming a CMOS device comprises: patterning a first mask over the memory array and over a first portion of the peripheral region; removing the protective layer that is exposed by the first mask and that comprises a second portion of the peripheral region; implanting the second portion of the peripheral region to form an NMOS device; patterning a second mask over the memory array and over the second portion of the peripheral region; removing the protective layer that is exposed by the second mask and that comprises the first portion of the peripheral region; and implanting the first portion of the peripheral region to form a PMOS device.
Claim 20
Dependent Claim
30 words
The process according to claim 15 , wherein forming a CMOS device comprises: forming self-aligned silicide structures under conditions that resist formation of self-aligned silicide structures in the memory array.
Claim 21
Dependent Claim
30 words
The process according to claim 15 , wherein forming a CMOS device comprises: removing the protective layer from the peripheral region; and forming self-aligned silicide structures in the peripheral region.
Claim 22
Dependent Claim
48 words
The process according to claim 15 , following forming a protective layer, further comprising: forming a masking material over the memory array and over the peripheral region; patterning the masking material over the memory array; and etching through the masking material to further define the emitter active area.
Claim 23
Dependent Claim
58 words
The process according to claim 15 , wherein forming a contact hole further comprises: etching a via in at least one dielectric material to expose a contact surface in a substrate; implanting N-type dopant into the contact surface to form an N-type base; forming a barrier material in the via; and filling the via with a conductive material.
Claim 24
Dependent Claim
116 words
The process according to claim 15 , wherein forming a lower electrode comprises: forming the first recess under conditions that expose two active areas in a first direction and at least two active areas in a second direction that is orthogonal to the first direction; forming a polysilicon film in the first recess; doping a portion of the polysilicon film in a first direction to achieve a first conductivity at the bottom of the first recess and a second conductivity in the first direction; and doping a portion of the polysilicon film in a second direction to maintain the first conductivity at the bottom of the first recess and the second conductivity in the second direction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-07-14 | 2007-01-13 | 2007-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-07-14 | 2011-01-13 | 2011-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-07-14 | 2015-01-13 | 2015-07-15 | $7700.00 | Window Closed / Lapsed |