Method for engineering the threshold voltage of a device using buried wells

Claim 1

A method for engineering the threshold voltage of a device, said method comprising: providing a substrate comprising a P-type bulk material, said substrate having a top surface and a bottom surface; forming a first NFET transistor in said substrate, said first NFET transistor comprising: a first N-type source region formed in said substrate; a first N-type drain region formed in said substrate; a first active region between and below said first N-type source and said first N-type drain; a first gate electrode formed over said first active region, wherein; said first NFET has a first threshold voltage; and forming a second NFET transistor in said substrate, said second NFET transistor comprising: a second N-type source region formed in said substrate; a second N-type drain region formed in said substrate; a second active region between and below said second N-type source and said second N-type drain; a second gate electrode formed over said active region; and a buried platform well formed below said second active region, wherein; said buried platform well is specifically formed such that a portion of dopant comprising said buried platform well is implanted in said second active region, thereby intentionally changing a second threshold voltage of said second NFET transistor with respect to said first threshold voltage of said first NFET transistor.

Claim 2

A method for engineering the threshold voltage of a device, said method comprising: providing a substrate comprising a P-type bulk material, said substrate having a top surface and a bottom surface; forming a first NFET transistor in said substrate, said first NFET transistor comprising: a first N-type source region formed in said substrate; a first N-type drain region formed in said substrate; a first active region between and below said first N-type source and said first N-type drain; a first gate electrode formed over said first active region, wherein; said first NFET has a first threshold voltage; and forming a second NFET transistor in said substrate, said second NFET transistor comprising: a second N-type source region formed in said substrate; a second N-type drain region formed in said substrate; a second active region between and below said second N-type source and said second N-type drain; a second gate electrode formed over said active region; and a buried platform well formed below said second active region, wherein; said buried platform well is specifically formed such that a portion of dopant comprising said buried platform well is implanted in said second active region, thereby intentionally changing a second threshold voltage of said second NFET transistor with respect to said first threshold voltage of said first NFET transistor.

Claim 4

A method for engineering the threshold voltage of a device, said method comprising: providing a substrate comprising a P-type bulk material, said substrate having a top surface and a bottom surface; forming a first platform NFET transistor in said substrate, said first platform NFET transistor comprising: a first N-type source region formed in said substrate; a first N-type drain region formed in said substrate; a first active region between and below said first N-type source and said first N-type drain; a first gate electrode formed over said first active region; and a first buried platform well formed below said first active region, wherein; said first buried platform well is specifically formed such that a portion of dopant comprising said first buried platform well is implanted in said first active region, thereby intentionally changing a first threshold voltage of said first platform NFET transistor; forming a second platform NFET transistor in said substrate, said second platform NFET transistor comprising: a second N-type source region formed in said substrate; a second N-type drain region formed in said substrate; a second active region between and below said second N-type source and said second N-type drain; a second gate electrode formed over said active region; and a second buried platform well formed below said second active region, wherein; said second buried platform well is specifically formed such that a portion of dopant comprising said second buried platform well is implanted in said second active region, thereby intentionally changing a second threshold voltage of said second platform NFET transistor.

Claim 5

A method for engineering the threshold voltage of a device, said method comprising: providing a substrate comprising a P-type bulk material, said substrate having a top surface and a bottom surface; forming a first platform NFET transistor in said substrate, said first platform NFET transistor comprising: a first N-type source region formed in said substrate; a first N-type drain region formed in said substrate; a first active region between and below said first N-type source and said first N-type drain; a first gate electrode formed over said first active region; and a first buried platform well formed below said first active region, wherein; said first buried platform well is specifically formed such that a portion of dopant comprising said first buried platform well is implanted in said first active region, thereby intentionally changing a first threshold voltage of said first platform NFET transistor; forming a second platform NFET transistor in said substrate, said second platform NFET transistor comprising: a second N-type source region formed in said substrate; a second N-type drain region formed in said substrate; a second active region between and below said second N-type source and said second N-type drain; a second gate electrode formed over said active region; and a second buried platform well formed below said second active region, wherein; said second buried platform well is specifically formed such that a portion of dopant comprising said second buried platform well is implanted in said second active region, thereby intentionally changing a second threshold voltage of said second platform NFET transistor.

Claim 9

A method for engineering the threshold voltage of a device, said method comprising: providing a substrate comprising a P-type bulk material, said substrate having a top surface and a bottom surface; forming a first platform NFET transistor in said substrate, said first platform NFET transistor comprising: a first N-type source region formed in said substrate; a first N-type drain region formed in said substrate; a first active region between and below said first N-type source and said first N-type drain; a first gate electrode formed over said first active region; and a first buried platform N-well formed below said first active region, wherein; said first buried platform N-well is specifically formed such that a portion of dopant comprising said first buried platform N-well is implanted in said second active region, thereby intentionally lowering a threshold voltage of said first platform NFET transistor to a first threshold voltage; forming a second platform NFET transistor in said substrate, said second platform NFET transistor comprising: a second N-type source region formed in said substrate; a second N-type drain region formed in said substrate; a second active region between and below said second N-type source and said second N-type drain; a second gate electrode formed over said active region; and a second buried platform N-well formed below said second active region, wherein; said second buried platform N-well is specifically formed such that a portion of dopant comprising said second buried platform N-well is implanted in said second active region, thereby intentionally lowering a threshold voltage of said second platform NFET transistor to a second threshold voltage, further wherein; said first threshold voltage is engineered to be different form said second threshold voltage.

Claim 10

A method for engineering the threshold voltage of a device, said method comprising: providing a substrate comprising a P-type bulk material, said substrate having a top surface and a bottom surface; forming a first platform NFET transistor in said substrate, said first platform NFET transistor comprising: a first N-type source region formed in said substrate; a first N-type drain region formed in said substrate; a first active region between and below said first N-type source and said first N-type drain; a first gate electrode formed over said first active region; and a first buried platform N-well formed below said first active region, wherein; said first buried platform N-well is specifically formed such that a portion of dopant comprising said first buried platform N-well is implanted in said second active region, thereby intentionally lowering a threshold voltage of said first platform NFET transistor to a first threshold voltage; forming a second platform NFET transistor in said substrate, said second platform NFET transistor comprising: a second N-type source region formed in said substrate; a second N-type drain region formed in said substrate; a second active region between and below said second N-type source and said second N-type drain; a second gate electrode formed over said active region; and a second buried platform N-well formed below said second active region, wherein; said second buried platform N-well is specifically formed such that a portion of dopant comprising said second buried platform N-well is implanted in said second active region, thereby intentionally lowering a threshold voltage of said second platform NFET transistor to a second threshold voltage, further wherein; said first threshold voltage is engineered to be different form said second threshold voltage.

Claim 11

A method for engineering the threshold voltage of a device, said method comprising: providing a substrate comprising a P-type bulk material, said substrate having a top surface and a bottom surface; forming a first N-well in said substrate; forming a first PFET transistor in said first N-well, said first PFET transistor comprising: a first P-type source region formed in said first N-well; a first P-type drain region formed in said first N-well; a first active region in said first N-well between and below said first P-type source and said first P-type drain; a first gate electrode formed over said first active region, wherein; said first PFET has a first threshold voltage; and forming a second N-well in said substrate; forming a second PFET transistor in said second N-well, said second PFET transistor comprising: a second P-type source region formed in said second N-well; a second P-type drain region formed in said second N-well; a second active region in said second N-well between and below said second P-type source and said second P-type drain; a second gate electrode formed over said second active region; and a buried platform well formed below said second active region, wherein; said buried platform well is specifically formed such that a portion of dopant comprising said buried platform well is implanted in said second active region, thereby intentionally changing a second threshold voltage of said second PFET transistor with respect to said first threshold voltage of said first PFET transistor.

Claim 12

A method for engineering the threshold voltage of a device, said method comprising: providing a substrate comprising a P-type bulk material, said substrate having a top surface and a bottom surface; forming a first N-well in said substrate; forming a first PFET transistor in said first N-well, said first PFET transistor comprising: a first P-type source region formed in said first N-well; a first P-type drain region formed in said first N-well; a first active region in said first N-well between and below said first P-type source and said first P-type drain; a first gate electrode formed over said first active region, wherein; said first PFET has a first threshold voltage; and forming a second N-well in said substrate; forming a second PFET transistor in said second N-well, said second PFET transistor comprising: a second P-type source region formed in said second N-well; a second P-type drain region formed in said second N-well; a second active region in said second N-well between and below said second P-type source and said second P-type drain; a second gate electrode formed over said second active region; and a buried platform well formed below said second active region, wherein; said buried platform well is specifically formed such that a portion of dopant comprising said buried platform well is implanted in said second active region, thereby intentionally changing a second threshold voltage of said second PFET transistor with respect to said first threshold voltage of said first PFET transistor.

Claim 14

A method for engineering the threshold voltage of a device, said method comprising: providing a substrate comprising a P-type bulk material, said substrate having a top surface and a bottom surface; forming a first N-well in said substrate; forming a first platform PFET transistor in said first N-well, said first platform PFET transistor comprising: a first P-type source region formed in said first N-well; a first P-type drain region formed in said first N-well; a first active region in said first N-well between and below said first P-type source and said first P-type drain; a first gate electrode formed over said first active region; and a first buried platform well formed below said first active region, wherein; said first buried platform well is specifically formed such that a portion of dopant comprising said first buried platform well is implanted in said first active region, thereby intentionally changing a first threshold voltage of said first platform PFET transistor; forming a second N-well in said substrate: forming a second platform PFET transistor in said second N-well, said second platform PFET transistor comprising: a second P-type source region formed in said second N-well; a second P-type drain region formed in said second N-well; a second active region in said second N-well between and below said second P-type source and said second P-type drain; a second gate electrode formed over said second active region; and a second buried platform well formed below said second active region, wherein; said second buried platform well is specifically formed such that a portion of dopant comprising said second buried platform well is implanted in said second active region, thereby intentionally changing a second threshold voltage of said second platform PFET transistor.

Claim 15

A method for engineering the threshold voltage of a device, said method comprising: providing a substrate comprising a P-type bulk material, said substrate having a top surface and a bottom surface; forming a first N-well in said substrate; forming a first platform PFET transistor in said first N-well, said first platform PFET transistor comprising: a first P-type source region formed in said first N-well; a first P-type drain region formed in said first N-well; a first active region in said first N-well between and below said first P-type source and said first P-type drain; a first gate electrode formed over said first active region; and a first buried platform well formed below said first active region, wherein; said first buried platform well is specifically formed such that a portion of dopant comprising said first buried platform well is implanted in said first active region, thereby intentionally changing a first threshold voltage of said first platform PFET transistor; forming a second N-well in said substrate: forming a second platform PFET transistor in said second N-well, said second platform PFET transistor comprising: a second P-type source region formed in said second N-well; a second P-type drain region formed in said second N-well; a second active region in said second N-well between and below said second P-type source and said second P-type drain; a second gate electrode formed over said second active region; and a second buried platform well formed below said second active region, wherein; said second buried platform well is specifically formed such that a portion of dopant comprising said second buried platform well is implanted in said second active region, thereby intentionally changing a second threshold voltage of said second platform PFET transistor.

Claim 19

A method for engineering the threshold voltage of a device, said method comprising: providing a substrate comprising a P-type bulk material, said substrate having a top surface and a bottom surface; forming a first N-well in said substrate; forming a first platform PFET transistor in said first N-well, said first platform PFET transistor comprising: a first P-type source region formed in said first N-well; a first P-type drain region formed in said first N-well; a first active region in said first N-well between and below said first P-type source and said first P-type drain; a first gate electrode formed over said first active region; and a first buried platform N-well formed below said first active region, wherein; said first buried platform N-well is specifically formed such that a portion of dopant comprising said first buried platform N-well is implanted in said first active region, thereby intentionally raising a first threshold voltage of said first PFET transistor; forming a second N-well in said substrate; forming a second platform PFET transistor in said second N-well, said second platform PFET transistor comprising: a second P-type source region formed in said second N-well; a second P-type drain region formed in said second N-well; a second active region in said second N-well between and below said second P-type source and said second P-type drain; a second gate electrode formed over said second active region; and a second buried platform N-well formed below said second active region, wherein; said second buried platform N-well is specifically formed such that a portion of dopant comprising said second buried platform N-well is implanted in said second active region, thereby intentionally raising a second threshold voltage of said second PFET transistor, further wherein; said first threshold voltage is engineered to be different form said second threshold voltage.

Claim 20

A method for engineering the threshold voltage of a device, said method comprising: providing a substrate comprising a P-type bulk material, said substrate having a top surface and a bottom surface; forming a first N-well in said substrate; forming a first platform PFET transistor in said first N-well, said first platform PFET transistor comprising: a first P-type source region formed in said first N-well; a first P-type drain region formed in said first N-well; a first active region in said first N-well between and below said first P-type source and said first P-type drain; a first gate electrode formed over said first active region; and a first buried platform N-well formed below said first active region, wherein; said first buried platform N-well is specifically formed such that a portion of dopant comprising said first buried platform N-well is implanted in said first active region, thereby intentionally raising a first threshold voltage of said first PFET transistor; forming a second N-well in said substrate; forming a second platform PFET transistor in said second N-well, said second platform PFET transistor comprising: a second P-type source region formed in said second N-well; a second P-type drain region formed in said second N-well; a second active region in said second N-well between and below said second P-type source and said second P-type drain; a second gate electrode formed over said second active region; and a second buried platform N-well formed below said second active region, wherein; said second buried platform N-well is specifically formed such that a portion of dopant comprising said second buried platform N-well is implanted in said second active region, thereby intentionally raising a second threshold voltage of said second PFET transistor, further wherein; said first threshold voltage is engineered to be different form said second threshold voltage.

Claim 21

A method for engineering the threshold voltage of a device, said method comprising: providing a substrate comprising a P-type bulk material, said substrate having a top surface and a bottom surface; forming a first NFET transistor in said substrate, said first NFET transistor comprising: a first N-type source region formed in said substrate; a first N-type drain region formed in said substrate; a first active region between and below said first N-type source and said first N-type drain; a first gate electrode formed over said first active region, wherein; said first NFET has a first threshold voltage; forming a second NFET transistor in said substrate, said second NFET transistor comprising: a second N-type source region formed in said substrate; a second N-type drain region formed in said substrate; a second active region between and below said second N-type source and said second N-type drain; a second gate electrode formed over said active region; and a first buried platform well formed below said second active region, wherein; said first buried platform well is specifically formed such that a portion of dopant comprising said first buried platform well is implanted in said second active region, thereby intentionally changing a second threshold voltage of said second NFET transistor with respect to said first threshold voltage of said first NFET transistor; forming a first N-well in said substrate; forming a first PFET transistor in said first N-well, said first PFET transistor comprising: a first P-type source region formed in said first N-well; a first P-type drain region formed in said first N-well; a third active region in said first N-well between and below said first P-type source and said first P-type drain; a third gate electrode formed over said third active region, wherein; said first PFET transistor has a third threshold voltage; forming a second N-well in said substrate; forming a second PFET transistor in said second N-well, said second PFET transistor comprising: a second P-type source region formed in said second N-well; a second P-type drain region formed in said second N-well; a fourth active region in said second N-well between and below said second P-type source and said second P-type drain; a fourth gate electrode formed over said fourth active region; and a second buried platform well formed below said fourth active region, wherein; said second buried platform well is specifically formed such that a portion of dopant comprising said second buried platform well is implanted in said fourth active region, thereby intentionally changing a fourth threshold voltage of said second PFET transistor with respect to said third threshold voltage of said first PFET transistor.

Claim 22

A method for engineering the threshold voltage of a device, said method comprising: providing a substrate comprising a P-type bulk material, said substrate having a top surface and a bottom surface; forming a first NFET transistor in said substrate, said first NFET transistor comprising: a first N-type source region formed in said substrate; a first N-type drain region formed in said substrate; a first active region between and below said first N-type source and said first N-type drain; a first gate electrode formed over said first active region, wherein; said first NFET has a first threshold voltage; forming a second NFET transistor in said substrate, said second NFET transistor comprising: a second N-type source region formed in said substrate; a second N-type drain region formed in said substrate; a second active region between and below said second N-type source and said second N-type drain; a second gate electrode formed over said active region; and a first buried platform well formed below said second active region, wherein; said first buried platform well is specifically formed such that a portion of dopant comprising said first buried platform well is implanted in said second active region, thereby intentionally changing a second threshold voltage of said second NFET transistor with respect to said first threshold voltage of said first NFET transistor; forming a first N-well in said substrate; forming a first PFET transistor in said first N-well, said first PFET transistor comprising: a first P-type source region formed in said first N-well; a first P-type drain region formed in said first N-well; a third active region in said first N-well between and below said first P-type source and said first P-type drain; a third gate electrode formed over said third active region, wherein; said first PFET transistor has a third threshold voltage; forming a second N-well in said substrate; forming a second PFET transistor in said second N-well, said second PFET transistor comprising: a second P-type source region formed in said second N-well; a second P-type drain region formed in said second N-well; a fourth active region in said second N-well between and below said second P-type source and said second P-type drain; a fourth gate electrode formed over said fourth active region; and a second buried platform well formed below said fourth active region, wherein; said second buried platform well is specifically formed such that a portion of dopant comprising said second buried platform well is implanted in said fourth active region, thereby intentionally changing a fourth threshold voltage of said second PFET transistor with respect to said third threshold voltage of said first PFET transistor.

Claim 25

A method for engineering the threshold voltage of a device, said method comprising: providing a substrate comprising a P-type bulk material, said substrate having a top surface and a bottom surface; forming a first NFET transistor in said substrate, said first NFET transistor comprising: a first N-type source region formed in said substrate; a first N-type drain region formed in said substrate; a first active region between and below said first N-type source and said first N-type drain; and a first gate electrode formed over said first active region, wherein; said first NFET has a first threshold voltage; forming a second NFET transistor in said substrate, said second NFET transistor comprising: a second N-type source region formed in said substrate; a second N-type drain region formed in said substrate; a second active region between and below said second N-type source and said second N-type drain; a second gate electrode formed over said active region; and a first buried platform N-well formed below said second active region, wherein; said first buried platform N-well is specifically formed such that a portion of dopant comprising said first buried platform well is implanted in said second active region, thereby intentionally lowering a second threshold voltage of said second NFET transistor with respect to said first threshold voltage of said first NFET transistor; forming a first N-well in said substrate; forming a first PFET transistor in said first N-well, said first PFET transistor comprising: a first P-type source region formed in said first N-well; a first P-type drain region formed in said first N-well; a third active region in said first N-well between and below said first P-type source and said first P-type drain; a third gate electrode formed over said third active region, wherein; said first PFET has a third threshold voltage; forming a second N-well in said substrate; forming a second PFET transistor in said second N-well, said second PFET transistor comprising: a second P-type source region formed in said second N-well; a second P-type drain region formed in said second N-well; a fourth active region in said second N-well between and below said second P-type source and said second P-type drain; a fourth gate electrode formed over said fourth active region; and a second buried platform N-well formed below said fourth active region, wherein; said second buried platform N-well is specifically formed such that a portion of dopant comprising said second buried platform N-well is implanted in said fourth active region, thereby intentionally raising a fourth threshold voltage of said second PFET transistor with respect to said third threshold voltage of said first PFET transistor.

Claim 26

A method for engineering the threshold voltage of a device, said method comprising: providing a substrate comprising a P-type bulk material, said substrate having a top surface and a bottom surface; forming a first NFET transistor in said substrate, said first NFET transistor comprising: a first N-type source region formed in said substrate; a first N-type drain region formed in said substrate; a first active region between and below said first N-type source and said first N-type drain; and a first gate electrode formed over said first active region, wherein; said first NFET has a first threshold voltage; forming a second NFET transistor in said substrate, said second NFET transistor comprising: a second N-type source region formed in said substrate; a second N-type drain region formed in said substrate; a second active region between and below said second N-type source and said second N-type drain; a second gate electrode formed over said active region; and a first buried platform N-well formed below said second active region, wherein; said first buried platform N-well is specifically formed such that a portion of dopant comprising said first buried platform well is implanted in said second active region, thereby intentionally lowering a second threshold voltage of said second NFET transistor with respect to said first threshold voltage of said first NFET transistor; forming a first N-well in said substrate; forming a first PFET transistor in said first N-well, said first PFET transistor comprising: a first P-type source region formed in said first N-well; a first P-type drain region formed in said first N-well; a third active region in said first N-well between and below said first P-type source and said first P-type drain; a third gate electrode formed over said third active region, wherein; said first PFET has a third threshold voltage; forming a second N-well in said substrate; forming a second PFET transistor in said second N-well, said second PFET transistor comprising: a second P-type source region formed in said second N-well; a second P-type drain region formed in said second N-well; a fourth active region in said second N-well between and below said second P-type source and said second P-type drain; a fourth gate electrode formed over said fourth active region; and a second buried platform N-well formed below said fourth active region, wherein; said second buried platform N-well is specifically formed such that a portion of dopant comprising said second buried platform N-well is implanted in said fourth active region, thereby intentionally raising a fourth threshold voltage of said second PFET transistor with respect to said third threshold voltage of said first PFET transistor.