US5640115A
Expired / Lapsed
US
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Self-enabling latch
Assignee: Oracle America Inc
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Filing: 1995-12-01
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Granted: 1997-06-17
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Expires: 2015-12-01
Abstract
Abstract A self-enabling latch includes a pair of pass transistors, a pair of cross-coupled inverters, an EXCLUSIVE-NOR logic gate and a differential amplifier. The pass transistors receive a differential input data signal which is selectively latched by the cross-coupled inverters. The EXCLUSIVE-NOR logic gate also receives the input data signal and compares it with the latched data signal to provide a control signal for the amplifier. The control signal is active when the present input data is different from the previously latched data. The amplifier, enabled by the active control signal, amplifies a differential clock signal to provide an enabling signal for the pass transistors which thereby present the new input data to the cross-coupled inverters for latching.
Inventors
- 👤 Sameer D. Halepete
- 👤 James Burr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:41
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356052; H03K3/35606; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
119 words
An apparatus which includes a self-enabling latch, said self-enabling latch comprising: a data latch for receiving an input data signal and an enablement signal and in accordance therewith latching said input data signal for providing a latched data signal; and a latch controller, coupled to said data latch, for receiving a clock signal, said input data signal and said latched data signal and in accordance therewith providing said enablement signal; wherein said input data signal includes a first plurality of signal states and said latched data signal includes a second plurality of signal states, and wherein said data latch latches said input data signal only when said input data signal state is different from said latched data signal state.
Claim 2
Independent Claim
119 words
An apparatus which includes a self-enabling latch, said self-enabling latch comprising: a data latch for receiving an input data signal and an enablement signal and in accordance therewith latching said input data signal for providing a latched data signal; and a latch controller, coupled to said data latch, for receiving a clock signal, said input data signal and said latched data signal and in accordance therewith providing said enablement signal; wherein said input data signal includes a first plurality of signal states and said latched data signal includes a second plurality of signal states, and wherein said data latch latches said input data signal only when said input data signal state is different from said latched data signal state.
Claim 3
Dependent Claim
37 words
The apparatus of claim 1, wherein said enablement signal includes active and inactive signal states and is in said active signal state only when said input data signal state is different from said latched data signal state.
Claim 4
Dependent Claim
64 words
The apparatus of claim 1, wherein said data latch comprises: a pair of pass transistors for receiving said input data signal and said enablement signal and in accordance therewith providing an enabled data signal; and a pair of cross-coupled inverters, coupled to said pair of pass transistors, for receiving and latching said enabled data signal and in accordance therewith providing said latched data signal.
Claim 5
Dependent Claim
60 words
The apparatus of claim 1, wherein said latch controller comprises: a comparison circuit for receiving and comparing said input data signal and said latched data signal and in accordance therewith providing a control signal; and an enablement circuit, coupled to said comparison circuit, for receiving said clock signal and said control signal and in accordance therewith providing said enablement signal.
Claim 6
Dependent Claim
14 words
The apparatus of claim 4, wherein said comparison circuit comprises an EXCLUSIVE-NOR logic gate.
Claim 7
Dependent Claim
52 words
The apparatus of claim 4, wherein said enablement circuit comprises: a pass transistor for receiving said control signal and in accordance therewith providing a power signal; and a differential amplifier, coupled to said pass transistor, for receiving said power signal and said clock signal and in accordance therewith providing said enablement signal.
Claim 8
Dependent Claim
12 words
The apparatus of claim 1 wherein said apparatus is an integrated circuit.
Claim 9
Dependent Claim
11 words
The apparatus of claim 1 wherein said apparatus is a computer.
Claim 10
Independent Claim
126 words
A method of providing an apparatus including a self-enabling latch, said method comprising the steps of: providing a data latch for receiving an input data signal and an enablement signal and in accordance therewith latching said input data signal for providing a latched data signal; and providing a latch controller, coupled to said data latch, for receiving a clock signal, said input data signal and said latched data signal and in accordance therewith providing said enablement signal; wherein said input data signal includes a first plurality of signal states and said latched data signal includes a second plurality of signal states, and wherein said data latch latches said input data signal only when said input data signal state is different from said latched data signal state.
Claim 11
Independent Claim
126 words
A method of providing an apparatus including a self-enabling latch, said method comprising the steps of: providing a data latch for receiving an input data signal and an enablement signal and in accordance therewith latching said input data signal for providing a latched data signal; and providing a latch controller, coupled to said data latch, for receiving a clock signal, said input data signal and said latched data signal and in accordance therewith providing said enablement signal; wherein said input data signal includes a first plurality of signal states and said latched data signal includes a second plurality of signal states, and wherein said data latch latches said input data signal only when said input data signal state is different from said latched data signal state.
Claim 12
Dependent Claim
37 words
The method of claim 9, wherein said enablement signal includes active and inactive signal states and is in said active signal state only when said input data signal state is different from said latched data signal state.
Claim 13
Dependent Claim
70 words
The method of claim 9, wherein said step of providing a data latch comprises: providing a pair of pass transistors for receiving said input data signal and said enablement signal and in accordance therewith providing an enabled data signal; and providing a pair of cross-coupled inverters, coupled to said pair of pass transistors, for receiving and latching said enabled data signal and in accordance therewith providing said latched data signal.
Claim 14
Dependent Claim
66 words
The method of claim 9, wherein said step of providing a latch controller comprises: providing a comparison circuit for receiving and comparing said input data signal and said latched data signal and in accordance therewith providing a control signal; and providing an enablement circuit, coupled to said comparison circuit, for receiving said clock signal and said control signal and in accordance therewith providing said enablement signal.
Claim 15
Dependent Claim
19 words
The method of claim 12, wherein said step of providing a comparison circuit comprises providing an EXCLUSIVE-NOR logic gate.
Claim 16
Dependent Claim
58 words
The method of claim 12, wherein said step of providing an enablement circuit comprises: providing a pass transistor for receiving said control signal and in accordance therewith providing a power signal; and providing a differential amplifier, coupled to said pass transistor, for receiving said power signal and said clock signal and in accordance therewith providing said enablement signal.
Claim 17
Dependent Claim
15 words
The method of claim 9, wherein said self-enabling latch is included in an integrate circuit.
Claim 18
Dependent Claim
14 words
The method of claim 9, wherein said self-enabling latch is incorporated into a computer.
Claim 19
Independent Claim
108 words
A method of latching data in a self-enabling manner, said method comprising the steps of: receiving an input data signal and an enablement signal and in accordance therewith latching said input data signal for providing a latched data signal; and receiving a clock signal, said input data signal and said latched data signal and in accordance therewith providing said enablement signal; wherein said input data signal includes a first plurality of signal states and said latched data signal includes a second plurality of signal states, and wherein said input data signal is latched only when said input data signal state is different from said latched data signal state.
Claim 20
Independent Claim
108 words
A method of latching data in a self-enabling manner, said method comprising the steps of: receiving an input data signal and an enablement signal and in accordance therewith latching said input data signal for providing a latched data signal; and receiving a clock signal, said input data signal and said latched data signal and in accordance therewith providing said enablement signal; wherein said input data signal includes a first plurality of signal states and said latched data signal includes a second plurality of signal states, and wherein said input data signal is latched only when said input data signal state is different from said latched data signal state.
Claim 21
Dependent Claim
37 words
The method of claim 17, wherein said enablement signal includes active and inactive signal states and is in said active signal state only when said input data signal state is different from said latched data signal state.
Claim 22
Dependent Claim
69 words
The method of claim 17, wherein said step of receiving an input data signal and an enablement signal and in accordance therewith latching said input data signal for providing a latched data signal comprises: receiving said input data signal and said enablement signal and in accordance therewith providing an enabled data signal; and receiving and latching said enabled data signal and in accordance therewith providing said latched data signal.
Claim 23
Dependent Claim
68 words
The method of claim 17, wherein said step of receiving a clock signal, said input data signal and said latched data signal and in accordance therewith providing said enablement signal comprises: receiving and comparing said input data signal and said latched data signal and in accordance therewith providing a control signal; and receiving said clock signal and said control signal and in accordance therewith providing said enablement signal.
Claim 24
Dependent Claim
35 words
The method of claim 20, wherein said step of receiving and comparing said input data signal and said latched data signal and in accordance therewith providing a control signal comprises using an EXCLUSIVE-NOR logic gate.
Claim 25
Dependent Claim
55 words
The method of claim 20, wherein said step of receiving said clock signal and said control signal and in accordance therewith providing said enablement signal comprises: receiving said control signal and in accordance therewith providing a power signal; and receiving said power signal and said clock signal and in accordance therewith providing said enablement signal.
Claim 26
Dependent Claim
14 words
The method of claim 17, wherein the steps are performed within an integrated circuit.
Claim 27
Dependent Claim
13 words
The method of claim 17, wherein the steps are performed within a computer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-16 | 2000-12-16 | 2001-06-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-16 | 2004-12-16 | 2005-06-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-16 | 2008-12-16 | 2009-06-17 | $7700.00 | Window Closed / Lapsed |