US6310487B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit and testing method thereof
Assignee: Aquila Innovations Inc
•
Filing: 1999-04-06
•
Granted: 2001-10-30
•
Expires: 2019-04-06
Abstract
Abstract The invention provides a semiconductor integrated circuit wherein a PMOS 111 having a high threshold voltage is installed between a VDD line 101 and a VDDV line 103, and a NMOS 121 having a high threshold voltage is installed between a VSS line 102 and a VSSV line 104. The semiconductor integrated circuit comprises a logic gate circuit supplied with a power source voltage via the VDDV line 103 and the VSSV line 104, respectively, and made up of PMOSes 131 to 133, and NMOSes 141 to 143. A substrate terminal of the PMOSes 131 to 133, respectively, is connected to a pad 163 to which a suitable voltage can be supplied from outside while a substrate terminal of the NMOSes 141 to 143, respectively, is connected to a pad 164 to which a suitable voltage can be supplied from outside. The semiconductor integrated circuit with such a configuration is capable of improving a failure detection ratio at testing.
Inventors
- 👤 Koichi Yokomizo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:43
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2884
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
233 words
A semiconductor integrated circuit having a plurality of first conduction type MOS transistors and a plurality of second conduction type MOS transistors, said semiconductor integrated circuit comprising: a first power supply line for supplying a first power source voltage; a first MOS transistor included among the plurality of the first conduction type MOS transistors, having a gate electrode, a first electrode, and a second electrode, the first MOS transistor having a first threshold voltage and the first electrode being electrically connected to the first power supply line; a first pseudo power supply line electrically connected to the second electrode of the first MOS transistor; an internal logic circuit having at least a second MOS transistor included among the plurality of the first conduction type MOS transistors, having a substrate terminal, the internal logic circuit supplied with the first power source voltage via the first pseudo power supply line and the second MOS transistor having a second threshold voltage lower than the first threshold voltage, the second threshold voltage controlled according to a voltage inputted to the substrate terminal; and a first terminal electrically connected to the substrate terminal of the second MOS transistor, wherein the substrate terminal of the second MOS transistor is capable of supplying a voltage which changes the second threshold voltage of the second MOS transistor to a higher voltage when the first MOS transistor is in a conductive state.
Claim 2
Dependent Claim
233 words
A semiconductor integrated circuit having a plurality of first conduction type MOS transistors and a plurality of second conduction type MOS transistors, said semiconductor integrated circuit comprising: a first power supply line for supplying a first power source voltage; a first MOS transistor included among the plurality of the first conduction type MOS transistors, having a gate electrode, a first electrode, and a second electrode, the first MOS transistor having a first threshold voltage and the first electrode being electrically connected to the first power supply line; a first pseudo power supply line electrically connected to the second electrode of the first MOS transistor; an internal logic circuit having at least a second MOS transistor included among the plurality of the first conduction type MOS transistors, having a substrate terminal, the internal logic circuit supplied with the first power source voltage via the first pseudo power supply line and the second MOS transistor having a second threshold voltage lower than the first threshold voltage, the second threshold voltage controlled according to a voltage inputted to the substrate terminal; and a first terminal electrically connected to the substrate terminal of the second MOS transistor, wherein the substrate terminal of the second MOS transistor is capable of supplying a voltage which changes the second threshold voltage of the second MOS transistor to a higher voltage when the first MOS transistor is in a conductive state.
Claim 3
Dependent Claim
26 words
A semiconductor integrated circuit according to claim 1 , wherein the first power source voltage is applied to a substrate terminal of the first MOS transistor.
Claim 4
Dependent Claim
76 words
A semiconductor integrated circuit according to claim 2 , wherein the first MOS transistor is formed in a first well layer of the second conduction type, formed in a semiconductor substrate while the second MOS transistor is formed in a third well layer of the second conduction type, within a second well layer of the first conduction type, formed in the second conduction type semiconductor substrate, the first terminal being connected to the third well layer.
Claim 5
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 1 , wherein the first terminal is electrically connected to a substrate terminal of the first MOS transistor.
Claim 6
Dependent Claim
42 words
A semiconductor integrated circuit according to claim 4 , wherein the first and second MOS transistors are formed in a first well layer of the second conduction type, formed in a semiconductor substrate, the first terminal being connected to the first well.
Claim 7
Dependent Claim
226 words
A semiconductor integrated circuit according to claim 1 , the semiconductor integrated circuit further comprising: a second power supply line for supplying a second power source voltage which is different from the first power source voltage; a third MOS transistor included among the plurality of the second conduction type MOS transistors, the third MOS transistor having a gate electrode, a first electrode, and a second electrode, the first electrode being electrically connected to the second power supply line, the third MOS transistor having a third threshold voltage; and a second pseudo power supply line electrically connected to the second electrode of the third MOS transistor, the second pseudo power line supplying the second power source voltage to the internal logic circuit; wherein said internal logic circuit having at least a fourth MOS transistor of the plurality included among the second conduction type MOS transistors, the fourth MOS transistor having a substrate terminal and having a fourth threshold voltage lower than the third threshold voltage, and said semiconductor integrated circuit still further comprising a second terminal electrically connected to the substrate terminal of the fourth MOS transistor, wherein the substrate terminal of the fourth MOS transistor is capable of supplying a voltage which changes the fourth threshold voltage of the fourth MOS transistor to a higher voltage when the third MOS transistor is in a conductive state.
Claim 8
Dependent Claim
26 words
A semiconductor integrated circuit according to claim 6 , wherein the second power source voltage is applied to a substrate terminal of the third MOS transistor.
Claim 9
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 6 , wherein the second terminal is electrically connected to a substrate terminal of the third MOS transistor.
Claim 10
Dependent Claim
44 words
A semiconductor integrated circuit according to claim 6 , further the semiconductor integrated circuit comprising a fourth terminal connected to the second power supply line, said fourth terminal being electrically connected to the second terminal in state of a molding the semiconductor integrated circuit.
Claim 11
Dependent Claim
22 words
A semiconductor integrated circuit according to claim 9 , the second terminal electrically connected to the fourth terminal by a wire bonding.
Claim 12
Dependent Claim
22 words
A semiconductor integrated circuit according to claim 10 , the first terminal electrically connected to the third terminal by a wire bonding.
Claim 13
Dependent Claim
136 words
A method of testing a semiconductor integrated circuit, using the semiconductor integrated circuit as set forth in claim 6 , wherein the first and third MOS transistors are turned into a conducting state by supplying the first power supply line with the first power source voltage and supplying the second power supply line with the second power source voltage, respectively, and a voltage so as to increase a threshold voltage of the second MOS transistor is supplied to the substrate terminal of the second MOS transistor by use of the first terminal while a voltage so as to increase a threshold voltage of the fourth MOS transistor is supplied to the substrate terminal of the fourth MOS transistor by use of the second terminal before measuring a value of current flowing through the internal logic circuit.
Claim 14
Dependent Claim
67 words
A semiconductor integrated circuit according to claim 6 , said semiconductor integrated circuit having a third terminal electrically connected to the first power supply line and a fourth terminal electrically connected to the second power supply line, and the first terminal electrically connected to the third terminal and the second terminal electrically connected to the fourth terminal in a state of a molding the semiconductor integrated circuit.
Claim 15
Dependent Claim
45 words
A semiconductor integrated circuit according to claim 1 , further the semiconductor integrated circuit comprising a third terminal electrically connected to the first power supply line, said third terminal being electrically connected to the first terminal in state of a molding the semiconductor integrated circuit.
Claim 16
Dependent Claim
22 words
A semiconductor integrated circuit according to claim 14 , the first terminal electrically connected to the third terminal by a wire bonding.
Claim 17
Dependent Claim
88 words
A method of testing a semiconductor integrated circuit, using the semiconductor integrated circuit as set forth in claim 1 , wherein the first MOS transistor is turned into a conducting state by supplying the first power supply line with the first power source voltage, and a voltage so as to increase a threshold voltage of the second MOS transistor is supplied to the substrate terminal of the second MOS transistor by use of the first terminal before measuring a value of current flowing through the internal logic circuit.
Claim 18
Dependent Claim
230 words
A semiconductor integrated circuit having a plurality of first conduction type MOS transistors and a plurality of second conduction type MOS transistors, said semiconductor integrated circuit comprising: a first power supply line for supplying a first power source voltage; a first MOS transistor included among the plurality of the first conduction type MOS transistors, having a gate electrode, a first electrode and a second electrode, the first MOS transistor having a first threshold voltage and the first electrode being electrically connected to the first power supply line; a first pseudo power supply line electrically connected to the second electrode of the first MOS transistor; an internal logic circuit having at least a second MOS transistor included among the plurality of the first conduction type MOS transistors, having a substrate terminal, the internal logic circuit supplied with the first power source voltage via the first pseudo power supply line and inputted a clock signal, and the second MOS transistor having a second threshold voltage lower than the first threshold voltage; a test terminal receivable a test signal; and a voltage supplying circuit supplying a predetermined voltage to the substrate terminal of the second MOS transistor according to a predetermined logic level of the test signal received at the test terminal, wherein the logic circuit is inhibited from inputting the clock signal according to the predetermined logic level of the test signal.
Claim 19
Dependent Claim
230 words
A semiconductor integrated circuit having a plurality of first conduction type MOS transistors and a plurality of second conduction type MOS transistors, said semiconductor integrated circuit comprising: a first power supply line for supplying a first power source voltage; a first MOS transistor included among the plurality of the first conduction type MOS transistors, having a gate electrode, a first electrode and a second electrode, the first MOS transistor having a first threshold voltage and the first electrode being electrically connected to the first power supply line; a first pseudo power supply line electrically connected to the second electrode of the first MOS transistor; an internal logic circuit having at least a second MOS transistor included among the plurality of the first conduction type MOS transistors, having a substrate terminal, the internal logic circuit supplied with the first power source voltage via the first pseudo power supply line and inputted a clock signal, and the second MOS transistor having a second threshold voltage lower than the first threshold voltage; a test terminal receivable a test signal; and a voltage supplying circuit supplying a predetermined voltage to the substrate terminal of the second MOS transistor according to a predetermined logic level of the test signal received at the test terminal, wherein the logic circuit is inhibited from inputting the clock signal according to the predetermined logic level of the test signal.
Claim 20
Dependent Claim
195 words
A semiconductor integrated circuit according to claim 17 , the semiconductor integrated circuit further comprising: a second power supply line for supplying a second power source voltage different from the first power source voltage; a third MOS transistor included among the plurality of the second conduction type MOS transistors, the third MOS transistor having a gate electrode, a first electrode, and a second electrode, the first electrode being electrically connected to the second power supply line, the third MOS transistor having a third threshold voltage; and a second pseudo power supply line electrically connected to the second electrode of the third MOS transistor, the second pseudo power line supplying the second power source voltage to the internal logic circuit, wherein said internal logic circuit having at least a fourth MOS transistor of the plurality of the second conduction type MOS transistors, the fourth MOS transistor having a substrate terminal and having a fourth threshold voltage lower than the third threshold voltage, and wherein the voltage supplying circuit supplied a predetermined voltage to the substrate terminal of the fourth MOS transistor according to the predetermined logic level of the test signal received at the first terminal.
References Cited (Backward Citations)
JPH06334010A
Cited
JPH098645A
Cited
JPH0946212A
Cited
JPH0964715A
Cited
JPH09198870A
Cited
US5917333A
Cited
JPH09321600A
Cited
JPH1032481A
Cited
JPH10135814A
Cited
JPH10242839A
Cited
US5942910A
Cited
JPH10187270A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-10-29 | 2005-04-30 | 2005-10-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-10-29 | 2009-04-30 | 2009-10-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-10-29 | 2013-04-30 | 2013-10-30 | $7700.00 | Window Closed / Lapsed |