Metal-insulator-semiconductor device having reduced threshold voltage and high mobility for high speed/low-voltage operation

Claim 2

In a MIS device comprising a pair of first doped layers of a second conductivity type forming source/drain regions in a semiconductor base structure of a first conductivity type, and a gate electrode formed in a region between the first doped layers of the second conductivity type on a gate insulating film formed on the semiconductor base structure, the improvement comprising: a second doped layer of the first conductivity type formed in the surface of a channel region extending between the source/drain regions; a third doped layer of the second conductivity type formed so as to underlie the second doped layer of the first conductivity type; and a fourth doped layer of the first conductivity type formed so as to underlie the third doped layer of the second conductivity type and having an impurity concentration higher than that of the semiconductor base structure, wherein an inversion layer channel formed when a voltage is applied to the gate electrode is a surface channel formed in the second doped layer of the first conductivity type underlying the gate insulating film, wherein the source/drain regions are separated from the third doped layer, respectively, and wherein the thickness of the third doped layer of the second conductivity type is determined so that the third doped layer of the second conductivity type is depleted by the built-in potential of a pn junction formed between the second doped layer of the first conductivity type and the third doped layer of the second conductivity type and that between the fourth doped layer of the first conductivity type and the third doped layer of the second conductivity type.

Claim 3

A MIS device according to claim 1, wherein a fifth doped layer of the first conductivity type having an impurity concentration higher than that of the semiconductor base structure is formed at a predetermined distance from at least one of the opposite ends of the channel region of the third doped layer of the second conductivity type.

Claim 4

A MIS device according to claim 1, wherein the fourth doped layer of the first conductivity type is formed so as to extend under the channel region and not to extend under the source/drain regions.

Claim 5

A MIS device according to claim 1, wherein the first conductivity type consists of one of an n-type and a p-type conductivity and the second conductivity consists of the other one of the n-type and p-type conductivity.

Claim 6

A MIS device according to claim 1, wherein the first conductivity type is p-type conductivity and the second conductivity type is n-type conductivity.

Claim 7

A MIS device according to claim 1, wherein said second doped layer has a junction depth greater than that of the first doped layers forming the source/drain regions.

Claim 8

A MIS device according to claim 6, wherein the first conductivity type consists of one of an n-type and a p-type conductivity and the second conductivity consists of the other one of the n-type and p-type conductivity.

Claim 9

A MIS device according to claim 6, wherein the first conductivity type is p-type conductivity and the second conductivity type is n-type conductivity.

Claim 10

In a MIS transistor device comprising a pair of first doped layers of a second conductivity type forming source/drain regions at a main surface in a semiconductor body of a first conductivity type, and a gate electrode formed, through a gate insulating film, on a region above a base layer of said semiconductor body between the first doped layers of the second conductivity type, the improvement comprising: a second doped layer of the first conductivity type formed at said main surface in a channel region extending between the source/drain regions; a third doped layer of the second conductivity type formed so as to underlie the second doped layer of the first conductivity type; and a fourth doped layer of the first conductivity type formed so as to underlie the third doped layer of the second conductivity type and having an impurity concentration higher than that of the base layer, wherein an inversion layer channel formed when a voltage is applied to the gate electrode is a main surface channel formed in the second doped layer of the first conductivity type underlying the gate insulating film, wherein the source/drain regions are separated from the third doped layer, respectively, and wherein the thickness of the third doped layer of the second conductivity type is determined so that the third doped layer of the second conductivity type is depleted by the built-in potential of a pn junction formed between the second doped layer of the first conductivity type and the third doped layer of the second conductivity type and that between the fourth doped layer of the first conductivity type and the third doped layer of the second conductivity type.

Claim 11

In a MIS transistor device comprising a pair of first doped layers of a second conductivity type forming source/drain regions at a main surface in a semiconductor body of a first conductivity type, and a gate electrode formed, through a gate insulating film, on a region above a base layer of said semiconductor body between the first doped layers of the second conductivity type, the improvement comprising: a second doped layer of the first conductivity type formed at said main surface in a channel region extending between the source/drain regions; a third doped layer of the second conductivity type formed so as to underlie the second doped layer of the first conductivity type; and a fourth doped layer of the first conductivity type formed so as to underlie the third doped layer of the second conductivity type and having an impurity concentration higher than that of the base layer, wherein an inversion layer channel formed when a voltage is applied to the gate electrode is a main surface channel formed in the second doped layer of the first conductivity type underlying the gate insulating film, wherein the source/drain regions are separated from the third doped layer, respectively, and wherein the thickness of the third doped layer of the second conductivity type is determined so that the third doped layer of the second conductivity type is depleted by the built-in potential of a pn junction formed between the second doped layer of the first conductivity type and the third doped layer of the second conductivity type and that between the fourth doped layer of the first conductivity type and the third doped layer of the second conductivity type.

Claim 12

A MIS transistor device according to claim 9, wherein said semiconductor body constitutes a semiconductor substrate.

Claim 13

A MIS transistor device according to claim 10, wherein said second doped layer has a junction depth greater than that of the first doped layers forming the source/drain regions.

Claim 14

A MIS transistor device according to claim 10, wherein the first conductivity type consists of one of an n-type and a p-type conductivity and the second conductivity consists of the other one of the n-type and p-type conductivity.

Claim 15

A MIS transistor device according to claim 10, wherein the first conductivity type is p-type conductivity and the second conductivity type is n-type conductivity.

Claim 16

A MIS transistor device according to claim 11, wherein said fourth doped layer is substantially limited to a region in said semiconductor body beneath the channel region and between the source/drain regions.

Claim 17

A MIS transistor device according to claim 10, wherein said fourth doped layer is substantially limited to a region in said semiconductor body beneath the channel region and between the source/drain regions.

Claim 18

A MIS transistor device according to claim 11, wherein said fourth doped layer is extended to underlie the channel region and the source/drain regions.

Claim 19

A MIS transistor device according to claim 10, wherein said fourth doped layer is extended to underlie the channel region and the source/drain regions.

Claim 20

A MIS transistor device according to claim 9, wherein said base layer is a semiconductor substrate, and wherein the first through third doped layers are formed in an epitaxial layer, said epitaxial layer being constituted by said fourth semiconductor layer of the first conductivity type.

Claim 21

A MIS transistor device according to claim 18, wherein said second doped layer has a junction depth greater than that of the first doped layers forming the source/drain regions.

Claim 22

A MIS transistor device according to claim 19, wherein said fourth doped layer is extended to underlie the channel region and the source/drain regions.

Claim 23

A MIS transistor device according to claim 18, wherein said fourth doped layer is extended to underlie the channel region and the source/drain regions.

Claim 24

A MIS transistor device according to claim 18, wherein the first conductivity type consists of one of an n-type and a p-type conductivity and the second conductivity consists of the other one of the n-type and p-type conductivity.

Claim 25

A MIS transistor device according to claim 18, wherein the first conductivity type is p-type conductivity and the second conductivity type is n-type conductivity.

Claim 26

A MIS device constituted by at least one pair of complementary MIS transistors formed in respectively separate regions of a common semiconductor body, wherein each transistor has upper, first level doped layers for forming source/drain regions at a main surface of said semiconductor body, and a gate electrode formed, through a gate insulating film, on a region above a base layer in a corresponding portion of said semiconductor body between the source/drain regions of that MISFET, the improvement comprising: (i) in an isolated portion associated with a first transistor: a second doped layer of a first conductivity type formed at said main surface of a channel region extending between the source/drain regions, said source/drain regions having a second conductivity type; a third doped layer of the second conductivity type formed so as to underlie the second doped layer; and a fourth doped layer of the first conductivity type formed so as to underlie the third doped layer and having an impurity concentration higher than that of said base layer, wherein an inversion layer channel formed when a voltage is applied to the gate electrode is a main surface channel formed in the second doped layer, wherein the source/drain regions are separated from the third doped layer, respectively, and wherein the thickness of the third doped layer is determined so that the third doped layer is depleted by the built-in potential of a pn junction formed between the second doped layer and the third doped layer and that between the fourth doped layer and the third doped layer, and (ii) in an isolated portion associated with a second, complementary MIS transistor: a fifth doped layer of the second conductivity type formed at said main surface of a channel region extending between the source/drain regions, said source/drain regions having the first conductivity type; a sixth doped layer of the first conductivity type formed so as to underlie the fifth doped layer; and a seventh doped layer of the second conductivity type formed so as to underlie the sixth doped layer, wherein an inversion layer channel formed when a voltage is applied to the gate electrode is a main surface channel formed in the fifth doped layer, wherein the source/drain regions are separated from the sixth doped layer, respectively, and wherein the thickness of the sixth doped layer is determined so that the sixth doped layer is depleted by the built-in potential of a pn junction formed between the fifth doped layer and the sixth doped layer and that between the seventh doped layer and the sixth doped layer.

Claim 27

A MIS device constituted by at least one pair of complementary MIS transistors formed in respectively separate regions of a common semiconductor body, wherein each transistor has upper, first level doped layers for forming source/drain regions at a main surface of said semiconductor body, and a gate electrode formed, through a gate insulating film, on a region above a base layer in a corresponding portion of said semiconductor body between the source/drain regions of that MISFET, the improvement comprising: (i) in an isolated portion associated with a first transistor: a second doped layer of a first conductivity type formed at said main surface of a channel region extending between the source/drain regions, said source/drain regions having a second conductivity type; a third doped layer of the second conductivity type formed so as to underlie the second doped layer; and a fourth doped layer of the first conductivity type formed so as to underlie the third doped layer and having an impurity concentration higher than that of said base layer, wherein an inversion layer channel formed when a voltage is applied to the gate electrode is a main surface channel formed in the second doped layer, wherein the source/drain regions are separated from the third doped layer, respectively, and wherein the thickness of the third doped layer is determined so that the third doped layer is depleted by the built-in potential of a pn junction formed between the second doped layer and the third doped layer and that between the fourth doped layer and the third doped layer, and (ii) in an isolated portion associated with a second, complementary MIS transistor: a fifth doped layer of the second conductivity type formed at said main surface of a channel region extending between the source/drain regions, said source/drain regions having the first conductivity type; a sixth doped layer of the first conductivity type formed so as to underlie the fifth doped layer; and a seventh doped layer of the second conductivity type formed so as to underlie the sixth doped layer, wherein an inversion layer channel formed when a voltage is applied to the gate electrode is a main surface channel formed in the fifth doped layer, wherein the source/drain regions are separated from the sixth doped layer, respectively, and wherein the thickness of the sixth doped layer is determined so that the sixth doped layer is depleted by the built-in potential of a pn junction formed between the fifth doped layer and the sixth doped layer and that between the seventh doped layer and the sixth doped layer.

Claim 28

A MIS device according to claim 24, wherein said first and second MIS transistors are NMOS and PMOS transistors, respectively.

Claim 29

A MIS device according to claim 24, wherein the first conductivity type consists of one of an n-type and a p-type conductivity and the second conductivity consists of the other one of the n-type and p-type conductivity.