US6048746A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for making die-compensated threshold tuning circuit
Assignee: Oracle America Inc
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Filing: 1998-06-08
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Granted: 2000-04-11
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Expires: 2018-06-08
Abstract
Abstract To compensate for process, activity and environmental variations in a semiconductor device, a back-bias potential tuning circuit is formed on a semiconductor die. The tuning circuit tunes a bias potential applied to the semiconductor die to maintain a predetermined ratio between a transistor on-current and a transistor off-current through at least one channel region. Then, a leakage current is measured for multiple transistors formed in the semiconductor die to determine a representative leakage of the semiconductor die. Tuning characteristics of the back-bias potential tuning circuit are then set to match the representative leakage of the semiconductor die.
Inventors
- 👤 James B. Burr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:16
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/26; G01R31/27; G01R31/275; G01R31/2607; G01R31/2621
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
91 words
A method of forming a semiconductor device, comprising: forming a back-bias potential tuning circuit which tunes a bias potential applied to a semiconductor die to bring a threshold voltage of at least one channel region within the semiconductor die to a target value; measuring a leakage current of multiple transistors formed in the semiconductor die; determining a representative leakage of the semiconductor die from the measured leakage of the multiple transistors; and setting a tuning characteristic of the back-bias potential tuning circuit to match the representative leakage of the semiconductor die.
Claim 2
Independent Claim
91 words
A method of forming a semiconductor device, comprising: forming a back-bias potential tuning circuit which tunes a bias potential applied to a semiconductor die to bring a threshold voltage of at least one channel region within the semiconductor die to a target value; measuring a leakage current of multiple transistors formed in the semiconductor die; determining a representative leakage of the semiconductor die from the measured leakage of the multiple transistors; and setting a tuning characteristic of the back-bias potential tuning circuit to match the representative leakage of the semiconductor die.
Claim 3
Dependent Claim
34 words
A method as claimed in claim 1, wherein said setting a tuning characteristic includes selecting at least one of the multiple transistors for use as a test transistor in the back-bias potential tuning circuit.
Claim 4
Dependent Claim
28 words
A method as claimed in claim 1, wherein said setting a tuning characteristic includes mechanically trimming a width of a test transistor of the back-bias potential tuning circuit.
Claim 5
Dependent Claim
39 words
A method as claimed in claim 1, wherein said setting a tuning characteristic includes activating selected transistors among a bank of parallel connected transistors, and using the activated transistors as a test transistor of the back-bias potential tuning circuit.
Claim 6
Dependent Claim
119 words
A method as claimed in claim 1, wherein the back-bias potential tuning circuit includes a capacitor which is charged via a second transistor during an on-interval of the second transistor and which is discharged via a first transistor during an off-interval of the second transistor, wherein the back-bias potential tuning circuit brings the threshold voltage to the target voltage by measuring a voltage of the capacitor at a sampling time of the off-interval of the second transistor, and controlling a back-bias potential to bring the measured voltage to a target voltage, and wherein said setting a tuning characteristic includes setting the sampling time at which the voltage of the capacitor is measured during the off-interval of the second transistor.
Claim 7
Dependent Claim
80 words
A method as claimed in claim 1, wherein the back-bias potential tuning circuit brings the threshold voltage to the target voltage by measuring a current ratio between an on transistor and an off transistor within the semiconductor die, and controlling a back-bias potential to bring the measured current ratio to a target ratio, and wherein said setting a tuning characteristics includes setting a ratio between a channel width of the off transistor and a channel width of the on transistor.
Claim 8
Dependent Claim
17 words
A method as claimed in claim 6, wherein the target ratio is between 10 and 10,000 inclusive.
Claim 9
Dependent Claim
19 words
A method as claimed in claim 1, wherein the back-bias potential tuning circuit is formed on the semiconductor die.
Claim 10
Dependent Claim
19 words
A method as claimed in claim 1, wherein the back-bias potential tuning circuit is formed off the semiconductor die.
Claim 11
Independent Claim
99 words
A method of forming a semiconductor device comprising: forming a back-bias potential tuning circuit which tunes a bias potential applied to a semiconductor die to bring a threshold voltage of at least one channel region within the semiconductor die to a target value; subjecting the semiconductor die to worst case operating conditions and determining a target back-bias potential at which the semiconductor die is operational under the worst case operating conditions; and setting a tuning characteristic of the back-bias potential tuning circuit to cause the tuning circuit to generate the target back-bias potential under the worst case operating conditions.
Claim 12
Independent Claim
99 words
A method of forming a semiconductor device comprising: forming a back-bias potential tuning circuit which tunes a bias potential applied to a semiconductor die to bring a threshold voltage of at least one channel region within the semiconductor die to a target value; subjecting the semiconductor die to worst case operating conditions and determining a target back-bias potential at which the semiconductor die is operational under the worst case operating conditions; and setting a tuning characteristic of the back-bias potential tuning circuit to cause the tuning circuit to generate the target back-bias potential under the worst case operating conditions.
Claim 13
Dependent Claim
33 words
A method as claimed in claim 10, wherein said setting a tuning characteristic includes selecting at least one of multiple transistors for use as a test transistor in the back-bias potential tuning circuit.
Claim 14
Dependent Claim
28 words
A method as claimed in claim 10, wherein said setting a tuning characteristic includes mechanically trimming a width of a test transistor of the back-bias potential tuning circuit.
Claim 15
Dependent Claim
39 words
A method as claimed in claim 10, wherein said setting a tuning characteristic includes activating selected transistors among a bank of parallel connected transistors, and using the activated transistors as a test transistor of the back-bias potential tuning circuit.
Claim 16
Dependent Claim
119 words
A method as claimed in claim 10, wherein the back-bias potential tuning circuit includes a capacitor which is charged via a second transistor during an on-interval of the second transistor and which is discharged via a first transistor during an off-interval of the second transistor, wherein the back-bias potential tuning circuit brings the threshold voltage to the target voltage by measuring a voltage of the capacitor at a sampling time of the off-interval of the second transistor, and controlling a back-bias potential to bring the measured voltage to a target voltage, and wherein said setting a tuning characteristic includes setting the sampling time at which the voltage of the capacitor is measured during the off-interval of the second transistor.
Claim 17
Dependent Claim
76 words
A method as claimed in claim 10, wherein the back-bias potential tuning circuit brings the threshold voltage to the target voltage by measuring a current ratio between an on transistor and an off transistor, and controlling a back-bias potential to bring the measured current ratio to a target ratio, and wherein said setting a tuning characteristics includes setting a ratio between a channel width of the off transistor and a channel width of the on transistor.
Claim 18
Dependent Claim
18 words
A method as claimed in claim 15, wherein the target current ratio is between 10 and 10,000 inclusive.
Claim 19
Dependent Claim
19 words
A method as claimed in claim 10, wherein the back-bias potential tuning circuit is formed on the semiconductor die.
Claim 20
Dependent Claim
19 words
A method as claimed in claim 10, wherein the back-bias potential tuning circuit is formed off the semiconductor die.
References Cited (Backward Citations)
US4142114A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-04-11 | 2003-10-11 | 2004-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-04-11 | 2007-10-11 | 2008-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-04-11 | 2011-10-11 | 2012-04-11 | $7700.00 | Window Closed / Lapsed |