Patent US6324485B1 successfully refreshed from Google Patents.
US6324485B1
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Application specific automated test equipment system for testing integrated circuit devices in a native environment
Assignee: NEWMELLENNIA SOLUTIONS Inc
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Filing: 1999-01-26
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Granted: 2001-11-27
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Expires: 2019-01-26
Abstract
Abstract An application specific automated test equipment system for source synchronous bus interface devices is described. A native interface board is provided to interface an automated test unit and a device under test. The native interface board is configured with devices selected to recreate a native environment of the device under test. A first clock drives the devices on the native interface board. A second clock drives the device under test. The second clock signal is derived from the first clock signal to form a substitute clock signal that can be adjusted in relation to the first clock signal. Input and output timing relationships of the device under test are determined by altering the arrival time of the substitute clock at the device under test with respect to the timing of the first clock signal.
Inventors
- 👤 James M. Ellis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 07:18
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31905; G01R31/31917; G01R31/31922
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
143 words
An apparatus for testing an integrated circuit device in its native environment, the apparatus comprising: a test device; one or more native devices coupled to the test device, the one or more native devices selected and configured to recreate a native operating environment of the test device; a first clock circuit coupled to the one or more native devices and generating a first clock signal transmitted to the one or more native devices; and a second clock circuit comprising a timing control circuit coupled to the test device and generating a second clock signal transmitted to the test device, wherein the second clock signal is derived from the first clock signal, and wherein the timing control circuit comprises an amplitude adjustment circuit that is operable to adjust the amplitude of the second clock signal relative to the amplitude of the first clock signal.
Claim 2
Independent Claim
143 words
An apparatus for testing an integrated circuit device in its native environment, the apparatus comprising: a test device; one or more native devices coupled to the test device, the one or more native devices selected and configured to recreate a native operating environment of the test device; a first clock circuit coupled to the one or more native devices and generating a first clock signal transmitted to the one or more native devices; and a second clock circuit comprising a timing control circuit coupled to the test device and generating a second clock signal transmitted to the test device, wherein the second clock signal is derived from the first clock signal, and wherein the timing control circuit comprises an amplitude adjustment circuit that is operable to adjust the amplitude of the second clock signal relative to the amplitude of the first clock signal.
Claim 3
Dependent Claim
55 words
The apparatus of claim 1 wherein the one or more native devices are installed on an interface board coupled between the test device and an automated test equipment system, and wherein the native environment corresponds to an electrical and functional environment of the test device when the test device is used under normal operating conditions.
Claim 4
Dependent Claim
55 words
The apparatus of claim 2 further comprising a memory coupled to the interface board, the memory operable to store one or more test programs executable by the automated test equipment system to perform functional tests on the test device while the test device is operating functionally and electrically with the one or more native devices.
Claim 5
Dependent Claim
54 words
The apparatus of claim 3 wherein the one or more test programs includes a program to adjust a characteristic of the second clock signal relative to a corresponding characteristic of the first clock signal and to perform the functional tests on the test device while the characteristic is adjusted over a range of values.
Claim 6
Dependent Claim
28 words
The apparatus of claim 4 wherein one or more characteristics of the second clock signal is adjustable in relation to a corresponding characteristic of the first clock signal.
Claim 7
Dependent Claim
39 words
The apparatus of claim 4 wherein the timing control circuit comprises a time adjustment circuit that is operable to adjust a timing characteristic of the second clock signal relative to a corresponding timing characteristic of the first clock signal.
Claim 8
Dependent Claim
35 words
The apparatus of claim 6 wherein the time adjustment circuit includes a delay circuit that is configured to shift the phase of the second clock signal relative to the phase of the first clock signal.
Claim 9
Dependent Claim
34 words
The apparatus of claim 1 wherein the second clock circuit is placed in close proximity to the test device such that clock skew and clock signal degradation effects at the test device are minimized.
Claim 10
Dependent Claim
16 words
The apparatus of claim 8 wherein the test device comprises a source synchronous bus interface device.
Claim 11
Independent Claim
153 words
A system comprising: an automated test equipment unit; and an interface board coupled to the automated test equipment unit, the interface board comprising: a test device interface, one or more native devices coupled to the test device interface, the one or more native devices selected and configured to recreate a native electrical and functional environment of a test device coupled to the test device interface, a first clock circuit generating a first clock signal transmitted to the one or more native interface devices, and a second clock circuit comprising a timing control circuit generating a second clock signal transmitted to the test device coupled to the test device interface, wherein the second clock signal is derived from the first clock signal, and wherein the timing control circuit includes an amplifier circuit operable to shift an amplitude characteristic of the second clock signal relative to a corresponding amplitude characteristic of the first clock signal.
Claim 12
Independent Claim
153 words
A system comprising: an automated test equipment unit; and an interface board coupled to the automated test equipment unit, the interface board comprising: a test device interface, one or more native devices coupled to the test device interface, the one or more native devices selected and configured to recreate a native electrical and functional environment of a test device coupled to the test device interface, a first clock circuit generating a first clock signal transmitted to the one or more native interface devices, and a second clock circuit comprising a timing control circuit generating a second clock signal transmitted to the test device coupled to the test device interface, wherein the second clock signal is derived from the first clock signal, and wherein the timing control circuit includes an amplifier circuit operable to shift an amplitude characteristic of the second clock signal relative to a corresponding amplitude characteristic of the first clock signal.
Claim 13
Dependent Claim
55 words
The system of claim 10 further comprising a memory coupled to the interface board, the memory operable to store one or more test programs executable by the automated test equipment unit to perform functional tests on the test device while the test device is operating functionally and electrically with the one or more native devices.
Claim 14
Dependent Claim
54 words
The system of claim 11 wherein the one or more test programs includes a program to adjust a characteristic of the second clock signal relative to a corresponding characteristic of the first clock signal and to perform the functional tests on the test device while the characteristic is adjusted over a range of values.
Claim 15
Dependent Claim
40 words
The system of claim 12 wherein the one or more test programs are operable to write and read data to and from the test device and compare data written to the test device to data read from the test device.
Claim 16
Dependent Claim
56 words
The system of claim 13 wherein the one or more test programs comprise a test process, and wherein the test process is iteratively executed by successive read, write, and compare operations, each successive read, write, and compare operation followed by an incremental adjustment of a characteristic of the second clock signal propagated to the test device.
Claim 17
Dependent Claim
60 words
The system of claim 14 wherein the test process is conducted until the test device fails a test conducted by the one or more test programs, and wherein the number of iterative read, write, and compare operations is used to determine a margin of error for the test device in relation to a corresponding characteristic of the second clock signal.
Claim 18
Dependent Claim
38 words
The system of claim 13 further comprising a user computer coupled to the automated test unit, the user computer comprising a user interface receiving data input from a user and displaying information processed by the automated test unit.
Claim 19
Dependent Claim
31 words
The system of claim 16 wherein the timing control circuit includes a delay circuit operable to shift a timing characteristic of the second clock signal relative to the first clock signal.
Claim 20
Dependent Claim
16 words
The system of claim 17 wherein the test device comprises a source synchronous bus interface device.
Claim 21
Dependent Claim
26 words
The system of claim 18 wherein the timing characteristic comprises a phase of the second clock signal relative to a phase of the first clock signal.
Claim 22
Independent Claim
164 words
An apparatus for testing an integrated circuit device comprising: means for interfacing the integrated circuit device to an automated test equipment system, wherein the interface means includes one or more native devices selected and configured recreate a native operating environment of the integrated circuit device; means for propagating a first clock signal to the one or more native devices; means for deriving a second clock signal from the first clock signal and propagating the second clock signal to the integrated circuit device; means for writing input data to the integrated circuit device; means for reading output data from the integrated circuit device; means for determining whether the output data matches the input data in accordance with predetermined criteria; and means for changing a timing characteristic and an amplitude characteristic of the second clock signal relative to respective and corresponding timing and amplitude characteristics of the first clock signal until the output data fails to meet the predetermined criteria with respect to the input data.
Claim 23
Independent Claim
164 words
An apparatus for testing an integrated circuit device comprising: means for interfacing the integrated circuit device to an automated test equipment system, wherein the interface means includes one or more native devices selected and configured recreate a native operating environment of the integrated circuit device; means for propagating a first clock signal to the one or more native devices; means for deriving a second clock signal from the first clock signal and propagating the second clock signal to the integrated circuit device; means for writing input data to the integrated circuit device; means for reading output data from the integrated circuit device; means for determining whether the output data matches the input data in accordance with predetermined criteria; and means for changing a timing characteristic and an amplitude characteristic of the second clock signal relative to respective and corresponding timing and amplitude characteristics of the first clock signal until the output data fails to meet the predetermined criteria with respect to the input data.
Claim 24
Independent Claim
182 words
A method of testing an integrated circuit device comprising the steps of: providing an interface board to couple the integrated circuit device to an automated test equipment system, wherein the interface board includes one or more native devices selected and configured recreate a native operating environment of the integrated circuit device; propagating a first clock signal to the one or more native devices on the interface board; propagating a second clock signal to the integrated circuit device; writing input data to the integrated circuit device; reading output data from the integrated circuit device; determining whether the output data matches the input data in accordance with predetermined criteria; changing a timing characteristic of the second clock signal until the output data fails to meet the predetermined criteria with respect to the input data; and deriving the second clock signal from the first clock signal prior to the step of propagating the second clock signal to the integrated circuit device, and wherein an amplitude characteristic of the second clock signal is adjusted with respect to a corresponding amplitude characteristic of the first clock signal.
Claim 25
Independent Claim
182 words
A method of testing an integrated circuit device comprising the steps of: providing an interface board to couple the integrated circuit device to an automated test equipment system, wherein the interface board includes one or more native devices selected and configured recreate a native operating environment of the integrated circuit device; propagating a first clock signal to the one or more native devices on the interface board; propagating a second clock signal to the integrated circuit device; writing input data to the integrated circuit device; reading output data from the integrated circuit device; determining whether the output data matches the input data in accordance with predetermined criteria; changing a timing characteristic of the second clock signal until the output data fails to meet the predetermined criteria with respect to the input data; and deriving the second clock signal from the first clock signal prior to the step of propagating the second clock signal to the integrated circuit device, and wherein an amplitude characteristic of the second clock signal is adjusted with respect to a corresponding amplitude characteristic of the first clock signal.
Claim 26
Dependent Claim
59 words
The method of claim 21 further comprising the step of deriving the second clock signal from the first clock signal prior to the step of propagating the second clock signal to the integrated circuit device, and wherein the timing characteristic of the second clock signal is adjusted with respect to a corresponding timing characteristic of the first clock signal.
Claim 27
Dependent Claim
50 words
The method of claim 22 further comprising the step of iteratively reading, writing, and comparing data written to and read from the integrated circuit device until the integrated circuit device fails a memory test, and wherein the timing characteristic of the second clock is incrementally adjusted after each compare operation.
Claim 28
Dependent Claim
38 words
The method of claim 23 further comprising the step of using the number of iteratively performed reading, writing, and comparing operations to determine a margin of error for the integrated circuit device with respect to the timing characteristic.
Claim 29
Dependent Claim
17 words
The method of claim 24 wherein the integrated circuit device comprises a source synchronous bus interface device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-11-26 | 2005-05-28 | 2005-11-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-11-26 | 2009-05-28 | 2009-11-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-11-26 | 2013-05-28 | 2013-11-27 | $7700.00 | Window Closed / Lapsed |