US5701309A — Automated test equipment digital tester expansion…

Claim 1

Independent Claim 238 words

A scan-based logic test apparatus for use with an automated test equipment (ATE) digital tester which tests scan-based logic IC devices, said test apparatus being pluggable into a bus slot within a computer including a first permanent memory, said test apparatus comprising: coupling means for coupling said apparatus to said computer to permit access to scan-based pattern data stored in the first permanent memory of said computer, said scan-based pattern data including serial input pattern data and expected serial output pattern data; I/O interface control means, coupled to said coupling means, for interfacing said apparatus to said computer to permit retrieval of said scan-based pattern data from said first permanent memory and for interfacing said apparatus to said digital tester to permit said tester to supply control signals to said apparatus; an SRAM memory, coupled to said I/O interface control means, for storing said scan-based pattern data including serial input pattern data and expected serial output pattern data from said first permanent memory upon retrieval thereof by said I/O interface control means, and an IC device interface means for coupling said IC device to said SRAM memory and said I/O interface control means, such that said serial input pattern data is provided to said IC device and actual serial output pattern data is collected from said IC device for comparison with said expected serial output pattern data to make a pass/fail decision with respect to said IC device.

Claim 2

Dependent Claim 238 words

A scan-based logic test apparatus for use with an automated test equipment (ATE) digital tester which tests scan-based logic IC devices, said test apparatus being pluggable into a bus slot within a computer including a first permanent memory, said test apparatus comprising: coupling means for coupling said apparatus to said computer to permit access to scan-based pattern data stored in the first permanent memory of said computer, said scan-based pattern data including serial input pattern data and expected serial output pattern data; I/O interface control means, coupled to said coupling means, for interfacing said apparatus to said computer to permit retrieval of said scan-based pattern data from said first permanent memory and for interfacing said apparatus to said digital tester to permit said tester to supply control signals to said apparatus; an SRAM memory, coupled to said I/O interface control means, for storing said scan-based pattern data including serial input pattern data and expected serial output pattern data from said first permanent memory upon retrieval thereof by said I/O interface control means, and an IC device interface means for coupling said IC device to said SRAM memory and said I/O interface control means, such that said serial input pattern data is provided to said IC device and actual serial output pattern data is collected from said IC device for comparison with said expected serial output pattern data to make a pass/fail decision with respect to said IC device.

Claim 3

Dependent Claim 40 words

The scan-based logic test apparatus of claim 1 further comprising a DATA line coupled between said digital tester and said apparatus for permitting said apparatus to receive control vectors stored in a second permanent memory situated in said digital tester.

Claim 4

Dependent Claim 36 words

The scan-based logic test apparatus of claim 1 including a FAIL line at which a FAIL signal is provided by said apparatus to inform said digital tester when said comparison indicates failure of said IC device.

Claim 5

Dependent Claim 231 words

A scan-based logic test system for testing scan-based logic IC devices comprising: a computer including a bus slot for receiving an adapter card therein, said computer further including a first permanent memory for storing scan-based pattern data including serial input pattern data and expected serial output pattern data; an ATE digital tester including a second permanent memory; a scan-based logic test card situated in said bus slot, said test card including: I/O interface control means, coupled to said bus slot and said digital tester, for interfacing said card to said computer to permit retrieval of said scan-based pattern data from said first permanent memory and for interfacing said apparatus to said digital tester to permit said tester to supply control signals to said apparatus; an SRAM memory, coupled to said I/O interface control means, for storing said scan-based pattern data including serial input pattern data and expected serial output pattern data from said first permanent memory upon retrieval thereof by said I/O interface control means, and an IC device interface means for coupling an IC device to said SRAM memory and said I/O interface control means, such that said serial input pattern data is provided to said IC device and actual serial output pattern data is collected from said IC device for comparison with said expected serial output pattern data to make a pass/fail decision with respect to said IC device.

Claim 6

Dependent Claim 231 words

A scan-based logic test system for testing scan-based logic IC devices comprising: a computer including a bus slot for receiving an adapter card therein, said computer further including a first permanent memory for storing scan-based pattern data including serial input pattern data and expected serial output pattern data; an ATE digital tester including a second permanent memory; a scan-based logic test card situated in said bus slot, said test card including: I/O interface control means, coupled to said bus slot and said digital tester, for interfacing said card to said computer to permit retrieval of said scan-based pattern data from said first permanent memory and for interfacing said apparatus to said digital tester to permit said tester to supply control signals to said apparatus; an SRAM memory, coupled to said I/O interface control means, for storing said scan-based pattern data including serial input pattern data and expected serial output pattern data from said first permanent memory upon retrieval thereof by said I/O interface control means, and an IC device interface means for coupling an IC device to said SRAM memory and said I/O interface control means, such that said serial input pattern data is provided to said IC device and actual serial output pattern data is collected from said IC device for comparison with said expected serial output pattern data to make a pass/fail decision with respect to said IC device.

Claim 7

Dependent Claim 33 words

The scan-based logic test system of claim 4 wherein said second permanent memory in said digital tester stores control vectors for controlling the testing of IC devices by said scan-based logic test card.

Claim 8

Dependent Claim 18 words

The scan-based logic test system of claim 4 wherein said first permanent memory comprises a hard disk drive.

Claim 9

Dependent Claim 18 words

The scan-based logic test system of claim 4 wherein said second permanent memory comprises a hard disk drive.

Claim 10

Dependent Claim 18 words

The scan-based logic test system of claim 4 wherein said computer comprises an ISA compatible bus architecture computer.

Claim 11

Independent Claim 207 words

A method of providing additional pattern memory to an automated test equipment (ATE) digital tester which tests scan-based logic IC devices, said method comprising the steps of: providing a computer including a first permanent memory and a scan-based logic card installed therein, said card including an SRAM pattern memory for storing scan-based patterns therein, said card being couplable to said scan-based logic IC device; storing serial input pattern data and expected serial output pattern data in the first permanent memory in said computer; storing control vectors in a second permanent memory in said digital tester for initiating and controlling the transfer of serial input pattern data by said card to said IC device; transferring said serial input pattern data and said expected serial output pattern data in said first permanent memory to said SRAM pattern memory; said card inputting the serial input pattern data from said SRAM memory to said IC device in response to said control vectors from said ATE digital tester; said card receiving responsive serial output data from said IC device in response to said serial input pattern data, and comparing said responsive serial output data to said expected serial output pattern data to make a pass/fail decision with respect to said IC device.

Claim 12

Independent Claim 207 words

A method of providing additional pattern memory to an automated test equipment (ATE) digital tester which tests scan-based logic IC devices, said method comprising the steps of: providing a computer including a first permanent memory and a scan-based logic card installed therein, said card including an SRAM pattern memory for storing scan-based patterns therein, said card being couplable to said scan-based logic IC device; storing serial input pattern data and expected serial output pattern data in the first permanent memory in said computer; storing control vectors in a second permanent memory in said digital tester for initiating and controlling the transfer of serial input pattern data by said card to said IC device; transferring said serial input pattern data and said expected serial output pattern data in said first permanent memory to said SRAM pattern memory; said card inputting the serial input pattern data from said SRAM memory to said IC device in response to said control vectors from said ATE digital tester; said card receiving responsive serial output data from said IC device in response to said serial input pattern data, and comparing said responsive serial output data to said expected serial output pattern data to make a pass/fail decision with respect to said IC device.

Claim 13

Dependent Claim 38 words

The method of claim 9 further comprising the step of generating a test pattern for said IC logic device, said test pattern including said control vectors, said serial input pattern data and said expected serial output pattern data.

Claim 14

Dependent Claim 27 words

The method of claim 10 further comprising the step of separating said control vectors from said serial input pattern data and said expected serial output pattern data.

Claim 15

Dependent Claim 22 words

The method of claim 9 wherein the computer provided in said providing a computer step is an ISA compatible bus architecture computer.

Claim 16

Dependent Claim 22 words

The method of claim 9 wherein the first permanent memory provided in said providing a computer step is a hard disk drive.

Claim 17

Dependent Claim 23 words

The method of claim 9 wherein the second permanent memory provided in said storing said control vectors step is a hard disk drive.

Claim 18

Independent Claim 243 words

A method of providing additional pattern memory to an automated test equipment (ATE) digital tester which tests scan-based logic IC devices, said method comprising the steps of: providing a computer including a first permanent memory and a scan-based logic card installed therein, said card including SRAM pattern memory for storing scan-based patterns therein, said card being couplable to said scan-based logic IC device for which testing by said ATE digital tester is desired; generating a test pattern for said IC logic device, said test pattern including control vectors, serial input pattern data and expected serial output pattern data; separating said control vectors from said serial input pattern data and said expected serial output pattern data; storing said control vectors in a second permanent memory in said digital tester; storing said serial input pattern data and said expected serial output pattern data in the first permanent memory in said card; transferring said serial input pattern data and said expected serial output pattern data in said first permanent memory to said SRAM pattern memory; said card inputting the serial input pattern data from said SRAM memory to said IC device in response to said control vectors from said ATE digital tester; said card receiving responsive serial output data from said IC device in response to said serial input pattern data, and comparing said responsive serial output data to said expected serial output pattern data to make a pass/fail decision with respect to said IC device.

Claim 19

Independent Claim 243 words

A method of providing additional pattern memory to an automated test equipment (ATE) digital tester which tests scan-based logic IC devices, said method comprising the steps of: providing a computer including a first permanent memory and a scan-based logic card installed therein, said card including SRAM pattern memory for storing scan-based patterns therein, said card being couplable to said scan-based logic IC device for which testing by said ATE digital tester is desired; generating a test pattern for said IC logic device, said test pattern including control vectors, serial input pattern data and expected serial output pattern data; separating said control vectors from said serial input pattern data and said expected serial output pattern data; storing said control vectors in a second permanent memory in said digital tester; storing said serial input pattern data and said expected serial output pattern data in the first permanent memory in said card; transferring said serial input pattern data and said expected serial output pattern data in said first permanent memory to said SRAM pattern memory; said card inputting the serial input pattern data from said SRAM memory to said IC device in response to said control vectors from said ATE digital tester; said card receiving responsive serial output data from said IC device in response to said serial input pattern data, and comparing said responsive serial output data to said expected serial output pattern data to make a pass/fail decision with respect to said IC device.

Claim 20

Dependent Claim 22 words

The method of claim 15 wherein the computer provided in said providing a computer step is an ISA compatible bus architecture computer.

Claim 21

Dependent Claim 22 words

The method of claim 15 wherein the first permanent memory provided in said providing a computer step is a hard disk drive.

Claim 22

Dependent Claim 23 words

The method of claim 15 wherein the second permanent memory provided in said storing said control vectors step is a hard disk drive.

Claim 23

Independent Claim 94 words

A system for testing a scan-based logic integrated circuit device comprising; a digital tester having a connector for connecting signal lines to at least some external terminals of a device to be tested, and including means for storing control vectors; a scan test apparatus coupled to said digital tester and to at least one external terminal of said device to be tested, said test apparatus including means for storing scan test vectors; and means operable in said digital tester for enabling said scan test apparatus to download said scan test vectors into said device.

Claim 24

Independent Claim 94 words

A system for testing a scan-based logic integrated circuit device comprising; a digital tester having a connector for connecting signal lines to at least some external terminals of a device to be tested, and including means for storing control vectors; a scan test apparatus coupled to said digital tester and to at least one external terminal of said device to be tested, said test apparatus including means for storing scan test vectors; and means operable in said digital tester for enabling said scan test apparatus to download said scan test vectors into said device.

Claim 25

Dependent Claim 44 words

The system of claim 19 and including means in said scan test apparatus for comparing a data pattern generated by said device in response to said scan test vectors to an ideal data pattern and for producing output data indicative of the correlation therebetween.

Claim 26

Dependent Claim 29 words

The system of claim 20 and including means in said digital tester responsive to said output data for providing one of a pass and fail indication of said device.

Claim 27

Independent Claim 160 words

A method for testing a scan-based integrated circuit device on an automated tester comprising the steps of: separating the test signals into control signals and preselected data signals; storing the data signals in a computer separate from the tester; coupling the tester to the computer via a data link for transferring command signals from the tester to the computer and for transferring data signals between the computer and the tester; connecting a device to be tested to the tester; generating control signals in the tester to place the device in a test mode; transferring the stored data signals from the computer through the data link to the device; transferring output signals generated by the device in response to the data signals from the device to the computer via the data link; comparing the output signals in the computer to predetermined ideal output signals; and providing status signals to the tester from the computer in response to the step of comparing.

Claim 28

Independent Claim 160 words

A method for testing a scan-based integrated circuit device on an automated tester comprising the steps of: separating the test signals into control signals and preselected data signals; storing the data signals in a computer separate from the tester; coupling the tester to the computer via a data link for transferring command signals from the tester to the computer and for transferring data signals between the computer and the tester; connecting a device to be tested to the tester; generating control signals in the tester to place the device in a test mode; transferring the stored data signals from the computer through the data link to the device; transferring output signals generated by the device in response to the data signals from the device to the computer via the data link; comparing the output signals in the computer to predetermined ideal output signals; and providing status signals to the tester from the computer in response to the step of comparing.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2000-12-22	2001-06-23	2001-12-23	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2004-12-22	2005-06-23	2005-12-23	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2008-12-22	2009-06-23	2009-12-23	$7700.00	Window Closed / Lapsed

Automated test equipment digital tester expansion apparatus

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