WSI tester

Claim 1

A system for testing a device under test (DUT), having DUT I/O ports, with the DUT of the type including N identical logical circuit copies, each circuit copy including storage elements (SEs) and combinatorial elements (CEs) and with each logic circuit copy structured into circuit element groups (CEGs) including only CEs, with each CEG having a set of inputs coupled to input SEs and a single output, where each of the identical logical circuit copies are structured into identical, corresponding CEGs, said test system comprising: a first test machine including N identical, corresponding first CEGs from each of the N circuit copies; a first set of input SEs coupled to the input ports of said first CEGs of said first test machine; a first voting logic circuit, having N input ports and N output ports, for generating a logic output signal at said N output ports, with the logic state of the output signal equal to the logic state of the majority of input signals received at said first voting logic circuit input ports; first enabling means for controllably coupling the output port of each said first CEG in said first test machine to a respective one of the input ports of said first voting logic circuit; a first set of N outputs SEs, with each output SE having an input port coupled to a respective one of the output ports of said voting logic circuit; means for transferring the logic state stored in an SE in said first set of output SEs to the DUT I/O ports; means for generating a test vector for setting the input states of said first set of input SEs to test said first test machine for faults and for transferring said test vector to the DUT I/O ports; means for generating a pre-test output state, corresponding to said test vector, to set the output state of said first set of output SEs prior to fault testing and for transferring said pre-test output state to the DUT I/O ports; means for generating an expected value post test output state; means, coupled to the DUT I/O ports, for loading said test vector into the first set of input SEs; means, coupled to the DUT I/O ports, for setting the output state of the first set of output SEs to said pre-test output state; means, coupled to said first test machine, for clocking said first test machine through one machine cycle to generate a post-test output state; and means, coupled to said DUT I/O ports, for comparing said post-test output state with said expected value post test output state to determine whether said first test machine has a fault.

Claim 2

A system for testing a device under test (DUT), having DUT I/O ports, with the DUT of the type including N identical logical circuit copies, each circuit copy including storage elements (SEs) and combinatorial elements (CEs) and with each logic circuit copy structured into circuit element groups (CEGs) including only CEs, with each CEG having a set of inputs coupled to input SEs and a single output, where each of the identical logical circuit copies are structured into identical, corresponding CEGs, said test system comprising: a first test machine including N identical, corresponding first CEGs from each of the N circuit copies; a first set of input SEs coupled to the input ports of said first CEGs of said first test machine; a first voting logic circuit, having N input ports and N output ports, for generating a logic output signal at said N output ports, with the logic state of the output signal equal to the logic state of the majority of input signals received at said first voting logic circuit input ports; first enabling means for controllably coupling the output port of each said first CEG in said first test machine to a respective one of the input ports of said first voting logic circuit; a first set of N outputs SEs, with each output SE having an input port coupled to a respective one of the output ports of said voting logic circuit; means for transferring the logic state stored in an SE in said first set of output SEs to the DUT I/O ports; means for generating a test vector for setting the input states of said first set of input SEs to test said first test machine for faults and for transferring said test vector to the DUT I/O ports; means for generating a pre-test output state, corresponding to said test vector, to set the output state of said first set of output SEs prior to fault testing and for transferring said pre-test output state to the DUT I/O ports; means for generating an expected value post test output state; means, coupled to the DUT I/O ports, for loading said test vector into the first set of input SEs; means, coupled to the DUT I/O ports, for setting the output state of the first set of output SEs to said pre-test output state; means, coupled to said first test machine, for clocking said first test machine through one machine cycle to generate a post-test output state; and means, coupled to said DUT I/O ports, for comparing said post-test output state with said expected value post test output state to determine whether said first test machine has a fault.