US4546473A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Random pattern self test design
Assignee: International Business Machines Corp
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Filing: 1983-05-06
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Granted: 1985-10-08
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Expires: 2003-05-06
Abstract
Abstract A PLA is constructed to improve random testing. Section circuits are provided that permit disabling sections of the output lines that are called segments so that the circuit can be tested one segment at a time. Selection circuits are also provided for enabling the product term lines only one at a time. Thus, while random test signals are conventionally applied to the PLA input terminals for test, only a small portion of the PLA is enabled for the test. Control signals for the selection circuits are generated randomly so that the portion of the PLA that is tested is varied randomly.
Inventors
- 👤 Edward B. Eichelberger
- 👤 Eric Lindbloom
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:29
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716; H03K19/1772
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
290 words
An array logic device of the type having first and second orthogonal sets of lines, means for applying input signals to the lines of the first set, circuit elements located at selected crossover points of the array to establish a pattern of interconnections from the first set to the second set, means for translating signals on the second set of lines to device output signals, means for generating a first plurality of random test signals and means for applying said test signals to said first lines, and means for detecting a function of the signal on said second lines during a test, wherein an improvement for self-testing the logic device comprises, means for supplying a second plurality of random signals, and means responsive to the second plurality of random signals for selectively enabling the lines of the first set in a plurality of segments during a test, and a second array having third and fourth orthogonal sets of lines, said fourth set of lines being formed as extensions of the lines of the second set, circuit elements at intersections of the third and extension lines in a pattern to disable a plurality of said second lines according to signals on said third lines, means for supplying a third plurality of random signals, and means responsive to said third plurality of random signals for forming signals on said third lines to disable a plurality of said second lines during a test, said second and third random signal means being arranged to cooperate with said first random signal means for stepping the device through a predetermined sequence of random test states, whereby after a predetermined number of steps the state of the device can be compared with the state of good device.
Claim 2
Dependent Claim
290 words
An array logic device of the type having first and second orthogonal sets of lines, means for applying input signals to the lines of the first set, circuit elements located at selected crossover points of the array to establish a pattern of interconnections from the first set to the second set, means for translating signals on the second set of lines to device output signals, means for generating a first plurality of random test signals and means for applying said test signals to said first lines, and means for detecting a function of the signal on said second lines during a test, wherein an improvement for self-testing the logic device comprises, means for supplying a second plurality of random signals, and means responsive to the second plurality of random signals for selectively enabling the lines of the first set in a plurality of segments during a test, and a second array having third and fourth orthogonal sets of lines, said fourth set of lines being formed as extensions of the lines of the second set, circuit elements at intersections of the third and extension lines in a pattern to disable a plurality of said second lines according to signals on said third lines, means for supplying a third plurality of random signals, and means responsive to said third plurality of random signals for forming signals on said third lines to disable a plurality of said second lines during a test, said second and third random signal means being arranged to cooperate with said first random signal means for stepping the device through a predetermined sequence of random test states, whereby after a predetermined number of steps the state of the device can be compared with the state of good device.
Claim 3
Dependent Claim
82 words
The device of claim 1 wherein said means for applying input signals to the lines of the first set includes gates in the lines of the first set and wherein said means for enabling the lines of the first set comprises means for decoding said second plurality of random signals to form a plurality of control signals and means connecting each of said control signals to a plurality of said gates to enable a segment of the lines of the first set.
Claim 4
Dependent Claim
56 words
The device of claim 2 wherein the device includes binary signal means defining a test operation or a normal operation and wherein said means for enabling the lines of the first set includes means connecting said gates to respond to said binary signal for enabling all of the lines of the first set for normal operation.
Claim 5
Dependent Claim
45 words
The device of claim 3 wherein said device includes a plurality of two-bit decoders comprising said gates and wherein said means connecting said control signals to said gates includes means connecting all of the gates of a two-bit decoder to receive the same control signal.
Claim 6
Dependent Claim
41 words
The device of claim 3 wherein the means responsive to said third plurality of random signals comprises means for decoding said third plurality of random signals and forming signals on said third lines to disable a plurality of said second lines.
Claim 7
Dependent Claim
35 words
The device of claim 5 wherein said circuit elements at said intersections of the third and extension lines are formed in a pattern to disable all but one of the second lines during a test.
Claim 8
Dependent Claim
70 words
The device of claim 6 wherein the means for decoding said third plurality of random signals comprises a plurality of two-bit decoders and wherein said circuit elements at said intersections of the third and extension lines are formed in a pattern to enable a line according to the occurance of a circuit element on a third line carrying a unique valued one of the four outputs of each two-bit decoder.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-10-07 | 1989-04-08 | 1989-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-10-07 | 1993-04-08 | 1993-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-10-07 | 1997-04-08 | 1997-10-08 | $7700.00 | Window Closed / Lapsed |