US4418410A
Expired / Lapsed
US
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Error detection and correction apparatus for a logic array
Assignee: International Business Machines Corp
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Filing: 1980-12-08
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Granted: 1983-11-29
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Expires: 2000-12-08
Abstract
Abstract Error detection and correction apparatus for a programmable logic array (PLA) having AND and OR logic combinations merged therein is disclosed. The output lines from the AND and OR logic elements are coupled in such a manner that their functions form complete groups containing, if possible, all minterms. Missing minterms are added, as necessary, by special output lines or logic elements provided for that purpose to complete a group. If a minterm occurs on two or more function lines, the corresponding minterm is entered as a correction term into an error detection logic means, one of which is associated with each group of logic output lines. The error detection logic means are also utilized to test whether one, and only one, of the output lines in a grouping of function lines has a binary 1 value. Error correction signals are generated by mixed group error detection means, the inputs of which are connected to a function line of another function group. If a single error is detected, the error detection logic means for the function line groups indicate which group includes the erroneous function line. The mixed group error detection means similarly indicate, if appropriate, which of function lines of the mixed group is erroneous.
Inventors
- 👤 Volkmar Goetze
- 👤 Dieter Schuett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:02
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/085; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
175 words
Error detection and correction apparatus for testing a binary logic array having at least one AND and one OR logic combination therein and a plurality of output lines, each of which output lines has an available function of said binary logic array present thereon, said apparatus including: (a) first circuit means, coupled to said binary logic array, for grouping the output function lines thereof so that each of said groups formed thereby include all possible minterms of the binary variables of that group and that all of the groups jointly include the totality of available binary functions of said binary logic array; (b) second circuit means, appropriately coupled to said first circuit means, for testing each of said groups of output function lines to determine whether one and only one function line in each of said groups has a binary value of one; and (c) third circuit means, appropriately coupled to said second circuit means, for generating an error signal at its output in response to said test which is indicative of the results thereof.
Claim 2
Dependent Claim
175 words
Error detection and correction apparatus for testing a binary logic array having at least one AND and one OR logic combination therein and a plurality of output lines, each of which output lines has an available function of said binary logic array present thereon, said apparatus including: (a) first circuit means, coupled to said binary logic array, for grouping the output function lines thereof so that each of said groups formed thereby include all possible minterms of the binary variables of that group and that all of the groups jointly include the totality of available binary functions of said binary logic array; (b) second circuit means, appropriately coupled to said first circuit means, for testing each of said groups of output function lines to determine whether one and only one function line in each of said groups has a binary value of one; and (c) third circuit means, appropriately coupled to said second circuit means, for generating an error signal at its output in response to said test which is indicative of the results thereof.
Claim 3
Dependent Claim
36 words
The apparatus according to claim 1 wherein said first circuit means includes fourth circuit means for adding any missing minterms to and thereby completing, if necessary, each of said groups formed by said first circuit means.
Claim 4
Dependent Claim
29 words
The apparatus according to claim 2 wherein said fourth circuit includes supplementary output function lines connected to the output of said binary logic array to provide said missing minterms.
Claim 5
Dependent Claim
87 words
The apparatus according to claim 1 wherein said first circuit means includes fourth circuit means for adding any missing minterms to and thereby completing, if necessary, each of said groups formed by said first circuit means, said missing minterms being added in such a manner that if an overlap is introduced thereby no error signal will be indicated by said third circuit means even though there will be a binary one signal present on the output function lines of said binary logic array affected by said overlap.
Claim 6
Dependent Claim
30 words
The apparatus according to claim 4 wherein said fourth circuit means includes supplementary output function lines connected to the output of said binary logic array to provide said missing minterms.
Claim 7
Dependent Claim
41 words
The apparatus according to claim 4 which also includes fifth circuit means, coupled between the output of said binary logic array and said second circuit means, for providing a correction signal path when there are overlaps in different output function lines.
Claim 8
Dependent Claim
68 words
The apparatus according to claim 6 which also includes sixth circuit means coupled to the output of said binary logic means, the input of said second circuit means and the input of said fifth circuit means, for generating a signal to be placed on said correction signal path when and only when an overlap would otherwise cause an error signal to be generated by said third circuit means.
Claim 9
Dependent Claim
20 words
The apparatus according to claim 7 wherein said fifth circuit means provides one correction signal path for each overlapping minterm.
Claim 10
Dependent Claim
76 words
The apparatus according to claim 1 which additionally comprises seventh circuit means, coupled to the output of said binary logic means and the input of said second circuit means, for providing a plurality of mixed groups of output function lines, each of said mixed groups consisting of an output function line from each of said groups regularly formed thereby, said mixed groups including all of the possible minterms of the binary variables of said logic array.
Claim 11
Dependent Claim
40 words
The apparatus according to claim 9 wherein said first circuit means includes fourth circuit means for adding any missing minterms to and thereby completing, if necessary, each of said groups formed by said first circuit means, including said mixed groups.
Claim 12
Dependent Claim
29 words
The apparatus according to claim 10 wherein said fourth circuit includes supplementary output function lines connected to the output of said binary logic array to provide said missing minterms.
Claim 13
Dependent Claim
42 words
The apparatus according to claim 11 wherein said seventh circuit means provides "r-1" mixed groups of output function lines where "r" is equal to the number of function lines in the regularly formed group having the greatest number of output function lines.
Claim 14
Dependent Claim
42 words
The apparatus according to claim 9 wherein said seventh circuit means provides "r-1" mixed groups of output function lines where "r" is equal to the number of function lines in the regularly formed group having the greatest number of output function lines.
Claim 15
Dependent Claim
92 words
The apparatus according to claim 1 which additionally comprises seventh circuit means, coupled to the output of said binary logic means and the input of said second circuit means, for providing a plurality of mixed groups of output function lines, each of said mixed groups consisting of a treelike structure of output function lines of the groups regularly formed thereby, the arrangement of each of said formed mixed group being a function of the complexity, number of output function lines and number of regularly formed groups thereof of said binary logic array.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-11-28 | 1987-05-30 | 1987-11-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-11-28 | 1991-05-30 | 1991-11-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-11-28 | 1995-05-30 | 1995-11-29 | $7700.00 | Window Closed / Lapsed |