Parallel path self-testing system

Claim 1

In a combinational and sequential logic circuit arranged on a plurality of logic units with memory circuits on each logic unit coupled together to form a shift register which shift register can be enabled to provide a shift register scan path for testing the logic circuit and disabled while the logic circuit is performing its designed logic function, apparatus for performing self-testing of the logic circuit using a multistage generator means to generate testing sequences for the self-testing and a multistage data compression means to compress the response of the logic circuits the improvement comprising: test circuit unit means containing the multistage random signal generator means for the generation of testing sequences and the multistage data compression means for the compression of the logic signals, circuit means coupling the scan paths of said logic units to said test circuit unit means and, logic means for coupling said shift register scan paths of said logic units in a plurality of parallel shift register paths between different stages of said signal generator means and said multistage data compression means for supplying said testing sequences to said memory circuits in said plurality of parallel paths so the response of said logic circuits is transmitted along said plurality of parallel paths to be compressed by said multistage data compression means for developing a self-test signature.