US6151356A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for phase detection in digital signals
Assignee: RPX Clearinghouse LLC
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Filing: 1998-09-17
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Granted: 2000-11-21
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Expires: 2018-09-17
Abstract
Abstract The invention provides an improved method and apparatus for detecting the phase difference between a digital data signal and a clock signal. By ensuring that no pulse in the output phase signal is narrow enough to introduce a non-linearity, the present invention avoids a source of non-linearity exhibited in existing phase detectors. In addition, by ensuring that critical timing paths through the circuit contain similar circuit blocks, with similar propagation delays, relative time relationships are preserved from clock and data inputs to XOR inputs. The circuit is therefore largely insensitive to changes in the characteristics of the components so long as they all move together, as they would in an integrated circuit implementation.
Inventors
- 👤 Robert William Spagnoletti
- 👤 Adrian Paul Sparks
- 👤 Stephen Richard Foster
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 00:35
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/091; H04L25/00; H04L25/02; H04L25/06; H04L25/061; H04L25/063; H04N; H04N7/00; H04N7/025; H04N7/035; H04N7/0352; H04L7/04; H04L7/041; H04L7/046
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
200 words
A digital signal phase detector comprising: a data signal input for receiving a data signal; a clock signal input for receiving a clock signal; a first circuit coupled to the data signal input and the clock signal input and arranged to provide a phase difference signal representative of both the clock period of the clock signal and the difference in phase between the clock signal and the data signal; a second circuit coupled to the first circuit and arranged to provide a reference signal representative of the clock period of the clock signal and duration of whose pulses is dependent only on the clock period of the clock signal; a third circuit coupled to receive the phase difference signal and responsive to extend by a predetermined amount the duration of signal pulses of the phase difference signal; and wherein a comparison of the phase difference signal with the reference signal provides an indication of the phase difference between the clock signal and the data signal and an indication of the magnitude of said phase difference; and wherein the indication of the magnitude of the phase difference between the clock signal and the data signal varies linearly with said phase difference.
Claim 2
Dependent Claim
200 words
A digital signal phase detector comprising: a data signal input for receiving a data signal; a clock signal input for receiving a clock signal; a first circuit coupled to the data signal input and the clock signal input and arranged to provide a phase difference signal representative of both the clock period of the clock signal and the difference in phase between the clock signal and the data signal; a second circuit coupled to the first circuit and arranged to provide a reference signal representative of the clock period of the clock signal and duration of whose pulses is dependent only on the clock period of the clock signal; a third circuit coupled to receive the phase difference signal and responsive to extend by a predetermined amount the duration of signal pulses of the phase difference signal; and wherein a comparison of the phase difference signal with the reference signal provides an indication of the phase difference between the clock signal and the data signal and an indication of the magnitude of said phase difference; and wherein the indication of the magnitude of the phase difference between the clock signal and the data signal varies linearly with said phase difference.
Claim 3
Dependent Claim
33 words
A detector according to claim 1 wherein the phase difference signal and the reference signal are provided responsive to only the rising or only the falling state transitions in the received data signal.
Claim 4
Dependent Claim
15 words
A detector according to claim 1 wherein the predetermined amount is half a clock cycle.
Claim 5
Dependent Claim
17 words
A detector according to claim 1 wherein: critical timing paths through the detector exhibit similar propagation delays.
Claim 6
Dependent Claim
212 words
A detector according to claim 1 comprising: data-reduction circuit means arranged to provide a reduced data output signal which changes state upon receipt of either only rising or only falling state transitions in a digital input signal; resynchronisation circuit means arranged to provide a resynchronised reduced data signal upon receipt of a clock input signal and the reduced data output signal; first shift register circuit means arranged to provide a first phase-shifted resynchronised reduced data signal upon receipt of the resynchronised reduced data signal and one or more clock signals; second shift register circuit means arranged to provide a second phase-shifted resynchronised reduced data signal upon receipt of the first phase-shifted resynchronised reduced data signal and one or more clock signals; first Exclusive OR circuit means arranged to provide a phase difference signal upon receipt of the reduced data signal and the first phase-shifted resynchronised reduced data signal; and second Exclusive OR circuit means arranged to provide a reference signal upon receipt of the resynchronised reduced data signal and the second phase-shifted resynchronised reduced data signal; and whereby, in operation, the difference between the phase difference signal and the reference signal varies linearly with the difference in phase between the data signal and the clock signal received by the resynchronisation circuit means.
Claim 7
Dependent Claim
28 words
A detector according to claim 5, wherein the data-reduction circuit means is arranged to respond to all rising or all falling state transitions in the digital input signal.
Claim 8
Dependent Claim
58 words
A detector according to claim 5 wherein: the data-reduction circuit means comprises a D-Type; the resynchronisation circuit means comprises a D-Type; the first shift register circuit means comprises a Latch; the second shift register circuit means comprises a Latch; the first XOR circuit means comprises an XOR gate; and the second XOR circuit means comprises an XOR gate.
Claim 9
Dependent Claim
43 words
A detector according to claims 5, wherein the moving time average of the difference between the phase difference signal and the reference signal varies linearly with the difference in phase between the data signal and the clock signal received by the resynchronisation circuit.
Claim 10
Dependent Claim
49 words
A detector according to claim 5 additionally comprising: integrating circuit means arranged to provide an integrated analogue signal which varies linearly with the phase difference between the data signal and the clock signal received by the resynchronisation circuit upon receipt of the phase difference signal and the reference signal.
Claim 11
Dependent Claim
56 words
A detector according to claim 5 additionally comprising: integrating circuit means arranged to provide an integrated analogue signal the moving time average of which varies linearly with the phase difference between the data signal and the clock signal received by the resynchronisation circuit, in response to receipt of the phase difference signal and the reference signal.
Claim 12
Dependent Claim
15 words
A detector according to claim 1 arranged to receive clock signals from a multi-phase clock.
Claim 13
Dependent Claim
61 words
A detector according to claim 1 additionally comprising: feedback circuit means arranged to provide a variable clock signal from which to derive the clock input signal, upon receipt of the phase difference signal and the reference signal; and retiming circuit means arranged to provide a retimed data signal in response to receipt of the data signal and the variable clock signal.
Claim 14
Dependent Claim
67 words
A detector according to claim 1 additionally comprising: feedback circuit means arranged to provide a variably-delayed data signal to be taken as the data signal received at the data signal input, upon receipt of the phase difference signal, the reference signal, and the data signal; and retiming circuit means arranged to provide a retimed data signal upon receipt of the variably-delayed data signal and the clock signal.
Claim 15
Independent Claim
142 words
A method of digital signal phase detection comprising the steps of: providing a data signal; providing a clock signal; providing a phase difference signal responsive to and representative of both the clock period of the clock signal and the difference in phase between the clock signal and data signal; providing a reference signal responsive to and representative of the clock period of the clock signal and duration of whose pulses is dependent only on the clock period of the clock signal; extending by a predetermined amount the duration of the signal pulses of the phase difference signal; and comparing the phase difference signal with the reference signal whereby to provide an indication of the phase difference between the clock signal and the data signal and an indication of the magnitude of said phase difference, which indication varies linearly with said phase difference.
Claim 16
Independent Claim
142 words
A method of digital signal phase detection comprising the steps of: providing a data signal; providing a clock signal; providing a phase difference signal responsive to and representative of both the clock period of the clock signal and the difference in phase between the clock signal and data signal; providing a reference signal responsive to and representative of the clock period of the clock signal and duration of whose pulses is dependent only on the clock period of the clock signal; extending by a predetermined amount the duration of the signal pulses of the phase difference signal; and comparing the phase difference signal with the reference signal whereby to provide an indication of the phase difference between the clock signal and the data signal and an indication of the magnitude of said phase difference, which indication varies linearly with said phase difference.
Claim 17
Independent Claim
186 words
The method of digital signal phase detection comprising the steps of: provision of a reduced data digital output signal which changes state upon receipt of either only rising or only falling state transitions in a digital input signal; resynchronisation to provide a resynchronised reduced data signal upon receipt of a clock input signal and the reduced data output signal; phase-shifting to provide a first phase-shifted resynchronised reduced data signal upon receipt of the resynchronised reduced data signal and one or more clock signals; phase-shifting to provide a second phase-shifted resynchronised reduced data signal upon receipt of the first phase-shifted resynchronised reduced data signal and one or more clock signals; provision of a phase difference signal being the exclusive OR of the reduced data signal and the first phase-shifted resynchronised reduced data signal; provision of a reference signal being the exclusive OR of the resynchronised reduced data signal and the second phase-shifted resynchronised reduced data signal; and whereby the difference between the phase difference signal and the reference signal varies linearly with the difference in phase between the data signal and the clock signal used in resynchronisation.
Claim 18
Independent Claim
186 words
The method of digital signal phase detection comprising the steps of: provision of a reduced data digital output signal which changes state upon receipt of either only rising or only falling state transitions in a digital input signal; resynchronisation to provide a resynchronised reduced data signal upon receipt of a clock input signal and the reduced data output signal; phase-shifting to provide a first phase-shifted resynchronised reduced data signal upon receipt of the resynchronised reduced data signal and one or more clock signals; phase-shifting to provide a second phase-shifted resynchronised reduced data signal upon receipt of the first phase-shifted resynchronised reduced data signal and one or more clock signals; provision of a phase difference signal being the exclusive OR of the reduced data signal and the first phase-shifted resynchronised reduced data signal; provision of a reference signal being the exclusive OR of the resynchronised reduced data signal and the second phase-shifted resynchronised reduced data signal; and whereby the difference between the phase difference signal and the reference signal varies linearly with the difference in phase between the data signal and the clock signal used in resynchronisation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-21 | 2004-05-22 | 2004-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-21 | 2008-05-22 | 2008-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-21 | 2012-05-22 | 2012-11-21 | $7700.00 | Window Closed / Lapsed |