Method and apparatus for a pulsed tri-state phase detector for reduced jitter clock recovery

Claim 3

The method of claim 1, wherein the detecting step (b) includes the steps of: (i) retiming the first data signal in accordance with a first clock edge to produce a first retimed data signal, and (ii) exclusive ORing the first retimed data signal with the first data signal to produce a second data signal indicative of the first transition edge of the first data signal.

Claim 4

The method of claim 2, wherein the outputting step (c) includes the steps of: (i) retiming the second data signal in accordance with the first clock edge to produce a second retimed data signal, (ii) retiming the second retimed data signal in accordance with a second clock edge to produce a third retimed data signal, and (iii) exclusive ORing the second retimed data signal with the third retimed data signal to output the reference pulse.

Claim 5

The method of claim 1, wherein the delaying step (d)(i) includes the step of delaying the first data signal for a period of time equal to approximately one-half of a clock period for transmitting the first data signal.

Claim 6

The method of claim 1, wherein the detecting step (b) includes the steps of: (i) retiming the first data signal in accordance with a first clock edge to produce a first retimed data signal, and (ii) exclusive ORing the first retimed data signal with the first data signal to produce a second data signal indicative of the first transition edge of the first data signal; and wherein the outputting step (c) includes the steps of: (i) retiming the second data signal in accordance with the first clock edge to produce a second retimed data signal, (ii) retiming the second retimed data signal in accordance with a second clock edge to produce a third retimed data signal, and (iii) exclusive ORing the second retimed data signal with the third retimed data signal to output the reference pulse.

Claim 7

The method of claim 1, wherein the detecting step (d)(ii) and the outputting step (d)(iii) include the steps of: (A) retiming the delayed data signal in accordance with a first clock edge to produce a first retimed data signal, and (B) exclusive ORing the delayed data signal with the first retimed data signal to output the variable width pulse.

Claim 8

The method of claim 6, wherein the detecting step (b) includes the steps of: (i) retiming the first data signal in accordance with a second clock edge to produce a first retimed data signal, and (ii) exclusive ORing the first retimed data signal with the first data signal to produce a second data signal indicative of the first transition edge of the first data signal; and wherein the outputting step (c) includes the steps of: (i) retiming the second data signal in accordance with the second clock edge to produce a second retimed data signal, (ii) retiming the second retimed data signal in accordance with first clock edge to produce a third retimed data signal, and (iii) exclusive ORing the second retimed data signal with the third retimed data signal to output the reference pulse.

Claim 9

A phase detector for outputting a variable width pulse indicative of phase and a reference pulse, comprising: (a) first circuitry for receiving a first data signal having a first transition edge and for detecting the first transition edge of the first data signal; (b) second circuitry, coupled to the first circuitry, for outputting a reference pulse in response to the detection of the first transition edge of the first data signal and in accordance with a first clock edge and a second clock edge; and (c) third circuitry, coupled to the first circuitry, for outputting a variable width pulse indicative of phase in response to the detection of the first transition edge of the first data signal, the third circuitry outputting the variable width pulse such that the variable width pulse overlaps in time with the reference pulse, and the variable width pulse and the reference pulse substantially cancel out one another when the phase detector is balanced, further wherein the third circuitry includes: (i) delay circuitry for delaying the first data signal for a period of time to produce a delayed data signal having a second transition edge, (ii) detection circuitry for detecting the second transition edge of the delayed data signal, and (iii) output circuitry for outputting the variable width pulse indicative of phase in response to the detection of the second transition edge of the delayed data signal and in accordance with the second clock edge such that the reference pulse and the variable width pulse are aligned along the second clock edge.

Claim 10

A phase detector for outputting a variable width pulse indicative of phase and a reference pulse, comprising: (a) first circuitry for receiving a first data signal having a first transition edge and for detecting the first transition edge of the first data signal; (b) second circuitry, coupled to the first circuitry, for outputting a reference pulse in response to the detection of the first transition edge of the first data signal and in accordance with a first clock edge and a second clock edge; and (c) third circuitry, coupled to the first circuitry, for outputting a variable width pulse indicative of phase in response to the detection of the first transition edge of the first data signal, the third circuitry outputting the variable width pulse such that the variable width pulse overlaps in time with the reference pulse, and the variable width pulse and the reference pulse substantially cancel out one another when the phase detector is balanced, further wherein the third circuitry includes: (i) delay circuitry for delaying the first data signal for a period of time to produce a delayed data signal having a second transition edge, (ii) detection circuitry for detecting the second transition edge of the delayed data signal, and (iii) output circuitry for outputting the variable width pulse indicative of phase in response to the detection of the second transition edge of the delayed data signal and in accordance with the second clock edge such that the reference pulse and the variable width pulse are aligned along the second clock edge.

Claim 11

The phase detector of claim 8, wherein the first circuitry (a) includes: (i) circuitry for retiming the first data signal in accordance with a first clock edge to produce a first retimed data signal, and (ii) an exclusive OR gate for exclusive ORing the first retimed data signal with the first data signal to produce a second data signal indicative of the first transition edge of the first data signal.

Claim 12

The phase detector of claim 9, wherein the second circuitry (b) includes: (i) circuitry for retiming the second data signal in accordance with the first clock edge to produce a second retimed data signal, (ii) circuitry for retiming the second retimed data signal in accordance with a second clock edge to produce a third retimed data signal, and (iii) an exclusive OR gate for exclusive ORing the second retimed data signal with the third retimed data signal to output the reference pulse.

Claim 13

The phase detector of claim 8, wherein the delay circuitry (c)(i) delays the first data signal for a period of time equal to approximately one-half of a clock period for transmitting the first data signal.

Claim 14

The phase detector of claim 8, wherein the first circuitry (a) includes: (i) circuitry for retiming the first data signal in accordance with a first clock edge to produce a first retimed data signal, and (ii) an exclusive OR gate for exclusive ORing the first retimed data signal with the first data signal to produce a second data signal indicative of the first transition edge of the first data signal; and wherein the second circuitry (b) includes: (i) circuitry for retiming the second data signal in accordance with the first clock edge to produce a second retimed data signal, (ii) circuitry for retiming the second retimed data signal in accordance with a second clock edge to produce a third retimed data signal, and (iii) an exclusive OR gate for exclusive ORing the second retimed data signal with the third retimed data signal to output the reference pulse.

Claim 15

The phase detector of claim 8, wherein the detection circuitry (c)(ii) and the output circuitry (c)(iii) include: (A) circuitry for retiming the delayed data signal in accordance with a first clock edge to produce a first retimed data signal, and (B) an exclusive OR gate for exclusive ORing the delayed data signal with the first retimed data signal to output the variable width pulse.

Claim 16

The phase detector of claim 13, wherein the first circuitry (a) includes: (i) circuitry for retiming the first data signal in accordance with a second clock edge to produce a first retimed data signal, and (ii) an exclusive OR gate for exclusive ORing the first retimed data signal with the first data signal to produce a second data signal indicative of the first transition edge of the first data signal; and wherein the second circuitry (b) includes: (i) circuitry for retiming the second data signal in accordance with the second clock edge to produce a second retimed data signal, (ii) circuitry for retiming the second retimed data signal in accordance with first clock edge to produce a third retimed data signal, and (iii) circuitry for exclusive ORing the second retimed data signal with the third retimed data signal to output the reference pulse.