Elastic buffer circuit

Claim 2

An elastic buffer circuit for converting data signals derived from burst data signals transmitted via a satellite to a ground communication system, which data signals are demodulated by a demodulator, into signals adapted to the timing of the ground communication system, comprising: synchronization code detecting means for detecting from an output of said demodulator a burst synchronization code and a received clock frequency and for supplying a detection signal; stable clock generating means for generating a first clock signal of a frequency equal to N (N is an integer not smaller than 2) times the received clock frequency; clock regenerating means for dividing the first clock signal by N and generating a second clock signal whose phase is determined by said detection signal; and data memory means responsive to said detection signal for starting a writing operation, and responsive to said second clock signal for temporarily storing said data signals following said burst synchronization code.

Claim 3

An elastic buffer circuit, as claimed in claim 1, wherein the second clock signal immediately follows the leading edge of said detection signal.

Claim 4

An elastic buffer circuit, as claimed in claim 1, wherein said clock regenerating means comprises: set/reset means; means responsive to said detection signal and said first clock signal for preparing a setting signal for said set/reset means; timing means responsive to the output signal of said set/reset means for generating a load pulse signal having a width equal to one clock of said first clock signal; counter means responsive to said load pulse signal for counting said first clock signal and generating said second clock signal; and reset pulse generating means responsive to an output signal of said set/reset means for generating a reset signal for said set/reset means.

Claim 5

An elastic buffer circuit for converting data signals derived from burst data signals transmitted via a satellite to a ground communication system, which data signals are demodulated by a demodulator, into signals adapted to the timing of the ground communication system, comprising: synchronization code detecting means for detecting from an output of said demodulator a burst synchronization code and a received clock frequency and for supplying a detection signal; delay means for delaying said data signals by a delay time equal to that of said synchronization code detecting means; stable clock generating means for generating a first clock signal of a frequency equal to N (N is an integer not smaller than 2) times the received clock frequency; clock regenerating means for dividing the first clock signal by N and generating a second clock signal whose phase is determined by said detection signal; first retiming means for synchronizing the delayed data signals following said burst synchronization code with said second clock signal; second retiming means for synchronizing said detecting signal with said second clock signal; and data memory means responsive to an output signal of said second retiming means for starting a writing operation and responsive to said second clock signal for temporarily storing an output signal of said first retiming means.

Claim 6

An elastic buffer circuit for converting data signals derived from burst data signals transmitted via a satellite to a ground communication system, which data signals are demodulated by a demodulator, into signals adapted to the timing of the ground communication system, comprising: synchronization code detecting means for detecting from an output of said demodulator a burst synchronization code and a received clock frequency and for supplying a detection signal; delay means for delaying said data signals by a delay time equal to that of said synchronization code detecting means; stable clock generating means for generating a first clock signal of a frequency equal to N (N is an integer not smaller than 2) times the received clock frequency; clock regenerating means for dividing the first clock signal by N and generating a second clock signal whose phase is determined by said detection signal; first retiming means for synchronizing the delayed data signals following said burst synchronization code with said second clock signal; second retiming means for synchronizing said detecting signal with said second clock signal; and data memory means responsive to an output signal of said second retiming means for starting a writing operation and responsive to said second clock signal for temporarily storing an output signal of said first retiming means.