US4270183A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data dejittering apparatus
Assignee: Lockheed Martin Corp
•
Filing: 1977-02-11
•
Granted: 1981-05-26
•
Expires: 1997-02-11
Abstract
Abstract A circuit for dejittering transmitted digital data. A buffer stores the incoming data and has its half-full condition monitored by content decoding circuitry including a counter whose count is converted to control the frequency of a voltage controlled oscillator. The oscillator clocks the data out of the buffer effectively free of harmful jitter.
Inventors
- 👤 Robert L. Robinson
- 👤 David C. Hoff
- 👤 Robert L. Midling
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 17:19
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; G; G06; G06F; G06F5/00; G06F5/06; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626; G06F2205/00; G06F2205/06; G06F2205/061
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
153 words
Dejittering apparatus for data comprising; a first-in, first-out buffer adapted to be clocked for receiving and outputting said data; input clocking means for clocking data into said buffer; output clocking means for clocking data out of said buffer; means for counting the amount of data clocked into said buffer by said input clocking means and for reducing said count in accordance with the amount of data clocked out by said output clocking means; half-full circuit means for developing a half-full signal indicating that said buffer is less than or greater than approximately half-full; counter synchronizing logic means responsive to said half-full signal for synchronizing said counter to the actual content of said buffer; means for converting the count of said counting means into a frequency control signal; and means responsive to said frequency control signal for controlling the rate at which data is clocked out of said buffer by said output clocking means.
Claim 2
Dependent Claim
153 words
Dejittering apparatus for data comprising; a first-in, first-out buffer adapted to be clocked for receiving and outputting said data; input clocking means for clocking data into said buffer; output clocking means for clocking data out of said buffer; means for counting the amount of data clocked into said buffer by said input clocking means and for reducing said count in accordance with the amount of data clocked out by said output clocking means; half-full circuit means for developing a half-full signal indicating that said buffer is less than or greater than approximately half-full; counter synchronizing logic means responsive to said half-full signal for synchronizing said counter to the actual content of said buffer; means for converting the count of said counting means into a frequency control signal; and means responsive to said frequency control signal for controlling the rate at which data is clocked out of said buffer by said output clocking means.
Claim 3
Dependent Claim
15 words
The apparatus of claim 1 wherein said buffer comprises a plurality of first-in, first-out registers.
Claim 4
Dependent Claim
37 words
The apparatus of claim 2 wherein said input clocking means comprises: a serial to parallel converter; and input sequencing means for clocking data into a first of said first-in, first-out registers from said serial to parallel converter.
Claim 5
Dependent Claim
37 words
The apparatus of claim 3 wherein said output clocking means comprises: a parallel to serial converter; and output sequencing means for clocking data from the last of said first-in, first-out registers into said parallel to serial converter.
Claim 6
Dependent Claim
37 words
The apparatus of claim 4 wherein said converting means comprises: a digital to analog converter fed by said counter; and filter means for producing said frequency control signal from the output of said digital to analog converter.
Claim 7
Dependent Claim
101 words
A dejittering apparatus for removing jitter from a stream of incoming data presented to said apparatus comprising: buffer means for receiving and storing the incoming data; means for clocking the data stored by said buffer means out of said buffer means; determining means for determining whether the amount of data is outside a defined range and for adjusting the frequency of said clocking means when said amount of data is outside of said range; and phase detector means responsive to said determing means for adjusting the frequency of said clocking means when said amount of data is within said defined range.
Claim 8
Dependent Claim
101 words
A dejittering apparatus for removing jitter from a stream of incoming data presented to said apparatus comprising: buffer means for receiving and storing the incoming data; means for clocking the data stored by said buffer means out of said buffer means; determining means for determining whether the amount of data is outside a defined range and for adjusting the frequency of said clocking means when said amount of data is outside of said range; and phase detector means responsive to said determing means for adjusting the frequency of said clocking means when said amount of data is within said defined range.
Claim 9
Dependent Claim
97 words
Dejittering apparatus for data comprising: buffer means for storing said data in accordance with the rate of an input clock and for outputting said data in response to an output clock; an adjustable frequency oscillator for supplying said output clock; means for averaging the input clock rate to adjust the frequency of said oscillator; means for monitoring said input clock to derive an indication of the amount of data in said buffer; and means for causing said averaging means to adjust the oscillator frequency if said amount of data in said buffer departs from a defined range.
Claim 10
Dependent Claim
97 words
Dejittering apparatus for data comprising: buffer means for storing said data in accordance with the rate of an input clock and for outputting said data in response to an output clock; an adjustable frequency oscillator for supplying said output clock; means for averaging the input clock rate to adjust the frequency of said oscillator; means for monitoring said input clock to derive an indication of the amount of data in said buffer; and means for causing said averaging means to adjust the oscillator frequency if said amount of data in said buffer departs from a defined range.
Claim 11
Dependent Claim
132 words
A dejittering apparatus for removing jitter from an incoming data stream presented to said apparatus comprising: buffer means for receiving, storing and outputting the data on a first-in, first-out basis, said buffer means comprising a plurality of cascade-coupled storage registers; input clocking means for providing an input clock for clocking the data into said buffer means; output clocking means for providing an output clock for clocking the data out of said buffer means; counting means for providing a count representative of the amount of data stored in said buffer means; converting means for converting said count of said counting means into a frequency control signal; and control means responsive to said frequency control signal for controlling the rate at which data is clocked out of said buffer means by said output clock.
Claim 12
Dependent Claim
132 words
A dejittering apparatus for removing jitter from an incoming data stream presented to said apparatus comprising: buffer means for receiving, storing and outputting the data on a first-in, first-out basis, said buffer means comprising a plurality of cascade-coupled storage registers; input clocking means for providing an input clock for clocking the data into said buffer means; output clocking means for providing an output clock for clocking the data out of said buffer means; counting means for providing a count representative of the amount of data stored in said buffer means; converting means for converting said count of said counting means into a frequency control signal; and control means responsive to said frequency control signal for controlling the rate at which data is clocked out of said buffer means by said output clock.
Claim 13
Dependent Claim
18 words
The dejittering apparatus of claim 8 wherein said counting means is controlled by said input and output clocks.
Claim 14
Dependent Claim
34 words
The dejittering apparatus of claim 9 wherein said counting means is an up/down counter having an up count input coupled to said input clock and a down count input coupled to said output clock.
Claim 15
Dependent Claim
52 words
The dejittering apparatus of claim 10 further comprising: half-full circuit means for generating a half-full signal indicating that said buffer means is less than or greater than approximately half-full of data; counter synchronizing means responsive to said half-full signal for synchronizing said up/down counter to the actual content of said buffer means.
Claim 16
Dependent Claim
34 words
The dejittering apparatus of claim 11 further comprising means for causing said counting means to produce a count representative of a half-full buffer means when data is not present on the incoming data stream.
Claim 17
Dependent Claim
46 words
The dejittering apparatus of claim 12 wherein the data stream is a serial data stream and wherein said input clocking means comprise: a serial to parallel converter; and input sequencing means for clocking data into a first of said registers from said serial to parallel converter.
Claim 18
Dependent Claim
36 words
The dejittering apparatus of claim 13 wherein said output clocking means comprises: a parallel to serial converter; and output sequencing means for clocking data from the last of said registers into said parallel to serial converter.
Claim 19
Dependent Claim
37 words
The apparatus of claim 14 wherein said converter means comprises: a digital to analog converter fed by said counter; and filter means for producing said frequency control signal from the output of said digital to analog converter.
References Cited (Backward Citations)
US3639689A
Cited
US3676583A
Cited
US3795872A
Cited
US3831189A
Cited
US3909843A
Cited
US3789379A
Cited
US3851335A
Cited
US3959815A
Cited
US3978519A
Cited
US4040027A
Cited
US4054921A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-05-25 | 1984-11-24 | 1985-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-05-25 | 1988-11-24 | 1989-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-05-25 | 1992-11-24 | 1993-05-26 | $7700.00 | Window Closed / Lapsed |