US3795872A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Protection scheme for clock signal recovery arrangement
Assignee: AT&T Inc
•
Filing: 1972-09-18
•
Granted: 1974-03-05
•
Expires: 1992-09-18
Abstract
Abstract Clocking signals are recovered from an incoming signal train by a master clock oscillator phase locked to the incoming signals and, in the event of failure of the master clock, by a standby clock similarly phase locked to the incoming signals. When an outage of the incoming signal is detected, or when it is presumed that the incoming signals are being improperly received, both clocks are unlocked from the incoming signals and the standby clock is phase locked to the output of the master. If there is subsequent phase slippage of the standby, it is unlocked from the master and both clocks run free. In one operational sequence, both clocks are again phase locked to the incoming signals if signal reception is restored.
Inventors
- 👤 O Napolitano
- 👤 G Pasternack
- 👤 B Saltzberg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 01:04
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/74; H03; H03L; H03L7/00; H03L7/06; H03L7/07
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
152 words
A system for recovering cloCk signals from an incoming signal train comprising: a first and a second local oscillator, each oscillator including means for phase locking the oscillator to signals applied to an input thereof and being arranged to run freely upon a blockage of the application of signals to the input, comparing means for detecting phase slippage between output signals of one of the two oscillators and the input signals, tracking means for detecting an excess of a predetermined difference in phase between output signals of the two oscillators, means for normally applying the incoming signal train to the input of each of the oscillators, and means responsive to the detection of phase slippage and to absence of the detection of the excessive phase difference for blocking the application of signals to the input of the first oscillator and phase locking the second oscillator to output signals of the first oscillator.
Claim 2
Independent Claim
152 words
A system for recovering cloCk signals from an incoming signal train comprising: a first and a second local oscillator, each oscillator including means for phase locking the oscillator to signals applied to an input thereof and being arranged to run freely upon a blockage of the application of signals to the input, comparing means for detecting phase slippage between output signals of one of the two oscillators and the input signals, tracking means for detecting an excess of a predetermined difference in phase between output signals of the two oscillators, means for normally applying the incoming signal train to the input of each of the oscillators, and means responsive to the detection of phase slippage and to absence of the detection of the excessive phase difference for blocking the application of signals to the input of the first oscillator and phase locking the second oscillator to output signals of the first oscillator.
Claim 3
Dependent Claim
48 words
A system, as in claim 1, wherein there is further included means effective when the second oscillator is phase locked to the first oscillator and responsive to phase slippage between the output signals of both oscillators for unlocking the second oscillator from the output of the first oscillator.
Claim 4
Dependent Claim
159 words
A clock recovery system wherein a master clock and a standby clock are phase locked to signals applied to inputs thereof and run freely upon a blockage of the application of signals to the inputs and outputs therefrom are applied to an output gating unit, CHARACTERIZED IN THAT the clock recovery system further includes: means for comparing the output of one clock to the output of the other clock to detect an excess of a predetermined difference in phase, means for comparing the output of each clock to the input signals thereof to detect phase slippage, means for normally applying an incoming signal train to the inputs of the master clock and standby clock, and logic means responsive to absence of the detection of the excessive phase difference and to the detection of phase slippage for blocking the application of input signals to the master clock and phase locking the standby clock to the output of the master clock.
Claim 5
Dependent Claim
159 words
A clock recovery system wherein a master clock and a standby clock are phase locked to signals applied to inputs thereof and run freely upon a blockage of the application of signals to the inputs and outputs therefrom are applied to an output gating unit, CHARACTERIZED IN THAT the clock recovery system further includes: means for comparing the output of one clock to the output of the other clock to detect an excess of a predetermined difference in phase, means for comparing the output of each clock to the input signals thereof to detect phase slippage, means for normally applying an incoming signal train to the inputs of the master clock and standby clock, and logic means responsive to absence of the detection of the excessive phase difference and to the detection of phase slippage for blocking the application of input signals to the master clock and phase locking the standby clock to the output of the master clock.
Claim 6
Dependent Claim
45 words
A clock recovery system, in accordance with claim 3, wherein there is further included logic means responsive to absence of the incoming signals for unlocking each clock from the incoming signal train and phase locking the standby clock to the output of the master clock.
Claim 7
Dependent Claim
38 words
A clock recovery system, in accordance with claim 4, wherein there is further included means responsive to restoration of the incoming signal train for again phase locking the master clock and the standby clock to the incoming signal.
Claim 8
Dependent Claim
62 words
A clock recovery system, in accordance with claim 4, wherein there is further included means effective when the standby clock is phase locked to the master clock and responsive to detection of phase slippage between the output of the standby clock and the output of the master clock for unlocking the standby clock from the master clock whereby both clocks run free.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-03-04 | 1977-09-03 | 1978-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-03-04 | 1981-09-03 | 1982-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-03-04 | 1985-09-03 | 1986-03-05 | $7700.00 | Window Closed / Lapsed |