Clock oscillator arrangements

Claim 2

In a clock oscillator system, in combination, first, second and third oscillator means each for selective operation as a master oscillator, each oscillator means comprising an oscillator having an output terminal and comparator means for producing an output signal in response to a predetermined phase difference between a pair of inputs thereto, the output terminal of each oscillator being connected as one input to its associated comparator means and control means for connecting one of said oscillator means for master oscillator operation while connecting the output terminal of the associated oscillator as the second input to each of the comparator means of the other oscillator means; and logic means for selecting one of said other oscillator means for master oscillator operation in response to an output signal from a comparator means associated with one of said other oscillator means, said logic means comprising three pairs of''''NAND'''' gates, each pair connected as a bistable circuit and each pair adapted to provide an output signal actuating said control means in dependence upon the state of the bistable circuit so formed, and means for changing the states of said ''''NAND'''' gate bistable circuits in response to an output from one of said comparator means.

Claim 3

The clock oscillator system as defined in claim 1 wherein said logic Means also includes three pairs of second NAND gates, one second NAND gate of each pair having one of the outputs of the first mentioned NAND gates as an input thereto while the other second NAND gate of each pair having another of the outputs of the first mentioned NAND gates as an input thereto, each pair of second NAND gates having a different combination of the outputs of said first mentioned NAND gates at inputs, and the two second NAND gates of each pair having common input associated with the output of one of said comparator means.

Claim 4

The clock oscillator system as defined in claim 1 including three normally open gates connecting the respective outputs of said comparator means to said pairs of second NAND gates as the respective common inputs thereto, and means for blocking all of said normally open gates in response to a comparator output signal passing any one of them.

Claim 5

The clock oscillator system as defined in claim 3 wherein the last means includes a bistable circuit.

Claim 6

The clock oscillator system as defined in claim 3 including a warning device associated with each oscillator means, and means for actuating a respective warning device in response to a comparator output passing any one of said normally open gates.

Claim 7

In a clock oscillator system, in combination, first, second and third oscillator means each for selective operation as a master oscillator, each oscillator means comprising an oscillator having an output terminal and comparator means for producing an output signal in response to a predetermined phase difference between a pair of inputs thereto, the output terminal of each oscillator being connected as one input to its associated comparator means, each comparator means including means for delaying said other input thereto, an OR function circuit receiving said one input and the delayed input, an integrating circuit receiving the output of said OR function circuit, and means for controlling the oscillator associated with the comparator means in response to the output of said integrating circuit, each comparator means also including means for producing said output signal thereof in response to output of said integrating circuit indicating said selected phase difference; control means for connecting one of said oscillator means for master oscillator operation while connecting the output terminal of the associated oscillator as the second input to each of the comparator means of the other oscillator means; logic means for selecting one of said other oscillator means for master oscillator operation in response to an output signal from that comparator means associated with the other of said other oscillator means; wherein said means for producing said output signal is a Schmitt trigger circuit.

Claim 8

In a clock oscillator system, in combination, first, second and third oscillator means each for selective operation as a master oscillator, each oscillator means comprising an oscillator having an output terminal and comparator means for producing an output signal in response to a predetermined phase difference between a pair of inputs thereto, the output terminal of each oscillator being connected as one input to its associated comparator means, each comparator means including means for delaying said other input thereto, an OR function circuit receiving said one input and the delayed input, an integrating circuit receiving the output of said OR function circuit, and means for controlling the oscillator associated with the comparator means in response to the output of said integrating circuit, each comparator means also including means for producing said output signal thereof in response to output of said integrating circuit indicating said selected phase difference; control means for connecting one of said oscillator means for master oscillator operation while connecting the output terminal of the associated oscillator as the second input to each of the comparator means of the other oscillator means; logic means for selecting one of said other oscillator means for master oscillator operation in response to an output signal from that comparator means associated with the other of said other oscillator means; wherein said means for producing said output signal is a Schmitt trigger circuit.