Buffer systems

Claim 2

A digital signal buffer unit comprising: a data signal shift register having a given number of shift stages interconnected to transfer digital signals one stage at a time from an input stage toward a last stage, each stage having output gating means, OR circuit means for receiving signals from all said gating means to pass signals from any shift stage as buffer output signals; an up/down counter having said given number, plus one, stable count indicating signal states, one of said states being a reference state with the remaining given number of said signal states indicating one of said shift stages, means connecting said up/down counter to said output gating means such that the respective output gating means is enabled by a one of said given number of indicating signal states; input data means for supplying data signals to said input stage and having input control means for supplying input control signals to simultaneously actuate said shift register to shift the signal content of said shift register one stage at a time toward said last stage and actuate said counter to count up; output data means for receiving said buffer output signals and having output control means supplying output control signals to said counter for actuating said counter to count down and said output control means simultaneously supplying one of said output control signals to said output gating means whereby the signal content of a given shift stage indicated by the signal state of said counter is read out from said given shift stage as a buffer output signal; and means responsive to simultaneous occurrence of said input and output control signals to inhibit said counter from changing signal states.

Claim 3

The digital signal buffer set forth in claim 1 further including in combination: alarm means connected to said up/down counter and responsive to said up/down counter reaching a predetermined count state to indicate a buffer error.

Claim 4

The digital signal buffer set forth in claim 1 further including in combination: clock means supplying timing pulses with a repetitive frequency at least as great as a maximum repetitive frequency of digital signal transfer; synchronizing signal transfer means electrically interposed between said data signal shift register and said input and output means and responsive to said timing pulses to time signal exchanges between said shift register and said input and output means; and counter control means responsive to said timing pulses and to said input and output means to selectively actuate said up/down counter in synchronism with said synchronizing signal transfer means.

Claim 5

The digital signal buffer set forth in claim 3 further including in combination: said clock means supplying A and B alternate successive timing pulses, one A and one B pulse being a timing cycle, said synchronizing signal transfer means and said counter control means being responsive to said B pulses and a portion of one of said data means being responsive to said A pulses such that said portion operates in alternate synchronism with said data signal shift register.

Claim 6

The digital signal buffer set forth in claim 4 wherein said one data means includes independent timing means for establishing bit periods wherein one data unit of signals is transferred, said bit period being of greater duration than said timing cycle; said synchronizing signal transfer means being responsive to said clock means and to each A pulse to signify that a data unit of signals is ready to be transferred at the next succeeding B Pulse time; and lockout means inhibiting plural successive signal transfers during a given bit period.

Claim 7

The digital signal buffer set forth in claim 5, further including in combination: an AND-OR circuit having input AND portions connected to said shift stages, respectively, and to said up/down counter for being enabled by the count states, respectively, except by said reference state.

Claim 8

Skew buffer apparatus having a given plurality of shift registers, each shift register having a first plurality of bistable elements, each element constituting a shift stage, and means for transferring signals between said stages from an input one of said stages toward a last one of said stages, and each stage having an output signal gate; the improvement including in combination: a given plurality of up/down counters, each of said up/down counters operatively associated with a corresponding one of said shift registers, each said up/down counter having a first plurality, plus one, of stable count-indicating states and a first output connection for each of said first plurality of stable count-indicating states and a plus-one output connection for said plus-one stable count-indicating state, said first output connections of each up/down counter respectively connected to said output signal gates of said corresponding shift registers for enabling same when said corresponding up/down counters are in the respective count-indicating state; a given plurality of data input means having data transfer means respectively connected to said input stage of each said corresponding shift register, plural input control means in each said data input means supplying control signals to said up/down counters, respectively, to actuate same to count up one state, to said data transfer means to simultaneously enable transfer of data signals to said respective input stage and to said shift register to shift the signal content thereof one stage toward said last stage; and a given plurality of data output means respectively receiving data signals from each said shift registers, a single output control means supplying control signals to all said up/down counters to count down by one state for enabling transferring data signals from shift stages respectively indicated by the respective up/down counter count-indicating signal state.

Claim 9

Skew buffer apparatus having a given plurality of shift registers, each shift register having a first plurality of bistable elements, each element constituting a shift stage, and means for transferring signals between said stages from an input one of said stages toward a last one of said stages, and each stage having an output signal gate; the improvement including in combination: a given plurality of up/down counters, each of said up/down counters operatively associated with a corresponding one of said shift registers, each said up/down counter having a first plurality, plus one, of stable count-indicating states and a first output connection for each of said first plurality of stable count-indicating states and a plus-one output connection for said plus-one stable count-indicating state, said first output connections of each up/down counter respectively connected to said output signal gates of said corresponding shift registers for enabling same when said corresponding up/down counters are in the respective count-indicating state; a given plurality of data input means having data transfer means respectively connected to said input stage of each said corresponding shift register, plural input control means in each said data input means supplying control signals to said up/down counters, respectively, to actuate same to count up one state, to said data transfer means to simultaneously enable transfer of data signals to said respective input stage and to said shift register to shift the signal content thereof one stage toward said last stage; and a given plurality of data output means respectively receiving data signals from each said shift registers, a single output control means supplying control signals to all said up/down counters to count down by one state for enabling transferring data signals from shift stages respectively indicated by the respective up/down counter count-indicating signal state.

Claim 10

The skew buffer apparatus set forth in claim 7 further including counter control means for each of said up/down counters, each said counter control means being responsive to said input control means control signals, respectively, and to said output control means control signal occurring simultaneously to inhibit count changes, and at all other times permit count changes in accordance with said control signals, respectively.

Claim 11

The skew buffer apparatus set forth in claim 8 further including clock means supplying A and B alternate successive timing pulses at a pulse repetitive frequency greater than expected data signal repetitive frequency; said data input means being responsive to said A timing pulses to signify data signals available; and a signal transfer circuit interposed between each said data input means and each said shift registers, respectively, and responsive to said A timing pulses to receive said data signals and each said input control means being responsive to received data and said B timing pulses to supply said input control signals, respectively.

Claim 12

The skew buffer system set forth in claim 9 wherein each said data input means comprises a readback channel of a multitrack magnetic tape recorder each generating a readback signal; VFC means in each said readback channel responsive to said readback signal in such readback channel to generate a bit period signal; detection means in each said readback channel jointly responsive to said bit period signal and said readback signal of such readback channel to supply a data signal; an interlock circuit in each said data input means signifYing data when conditioned, otherwise signifying not data; said input control means of each said data input means responsive to said bit period signal to condition said interlock circuit to signify that data can be received from said readback channels, respectively; data indicator means in each said input control means jointly responsive to said interlock means signifying data and said bit period signals, respectively, to supply said input control signals for the respective data input means; gating means responsive to said control signals and said data signals from the data input means, respectively, to insert said data signals into said shift registers, to decondition said interlock circuit, and to actuate said up/down counters, respectively; and said data indicating means responsive to each A pulse to assume a reset state.

Claim 13

The skew buffer system set forth in claim 10 wherein said clock means supplies about two cycles of A and B timing pulses per one of said bit periods; and each said output means being independently responsive to its associated up/down counter and to said output control means to transfer a signal from its connected shift register stage indicated by the corresponding active count state of such associated up/down counter.

Claim 14

The skew buffer apparatus set forth in claim 11 wherein each said output means comprises an AND-OR circuit, one AND input portion for each said shift stage and responsive to one of the count states to pass the signal content of said shift stages, respectively, to an output OR portion; and means simultaneously receiving signals from all said AND-OR circuits.

Claim 15

The skew buffer apparatus of claim 7, further including in combination: a magnetic tape transport apparatus having a multitrack head with recording and sensing portions for scanning tracks on a tape; utilization means for data signals; first and second double-throw multiple pole switching means each having center, read, and write connection means, common control means connected to both said switching means, for selectively respectively connecting said center to said read or write connection means of said switching means; said center connection means of said first switching means respectively connected to all said input data means; said read connection means of said first switching means respectively connected to said sensing portions; said write connection means of said first switching means respectively connected to said utilization means; said center connection of said second switching means respectively connected to said output data means; said read connection means of said second switching means respectively connected to said utilization means; and said write connection means of said second switching means respectively connected to said recording portions.

Claim 16

The apparatus of claim 13 further including in combination: clock means supplying alternate successive A and B timing pulses to time said utilization means and said input and output data means; and means in said input data means responsive to said B timing pulses to generate said control signals and to said A timing pulses to deactivate said input means until new data signals are available.

Claim 17

The skew buffer apparatus set forth in claim 7 wherein each said up/down counter has N stable counting states, N being an integer one greater than the number of shift stages in each said shift registers; each up/down counter having carry-out means for said Nth count state for supplying a carry-out signal; and alarm means responsive to any one of said carry-out means supplying a carry-out signal to indicate an error.

Claim 18

The skew buffer apparatus set forth in claim 15 further including carry-out means for each up/down counter for each N-X signal state, where X is a positive integer; and marginal skew means responsive to any N-X carry-out signal to signify a marginal erroR condition.

Claim 19

The skew buffer apparatus set forth in claim 7 further including count decoding means responsive to any said up/down counter having a count state of N (where N is an integer equal to the number of said shift stages in a shift register), plus one, and to one of said control signals to signify an error condition.

Claim 20

The skew buffer apparatus set forth in claim 17 further including means in said count decoding means responsive to any up/down counter having a count state of N-X, where X is a positive integer less than N to signify a marginal error condition.

Claim 21

Deskewing buffer circuits including in combination: a given plurality of shift registers each having a first plurality of shift stages, each stage having a shift register output means, one of said stages in each shift register being an input stage for such shift register; said given plurality of counters respectively operatively connected to said shift registers, one counter per shift register and each said counter selectively supplying an actuating signal to one of said register output means in the respective shift register in accordance with the signal content of said each counter; said given plurality of input means supplying control signals to said counters and shift registers, respectively, for simultaneously actuating said counters to increment by one and said shift register to shift its signal contents by one stage toward one end of each said respective shift registers, data means in said input means simultaneously supplying data signals to said shift registers for storing same in said shift registers, respectively; data output means for simultaneously receiving signals from any one stage in all said shift registers, said shift register output means in each said shift registers responsive to the signal content of the respective said counters to select said any one stage in accordance with the counter signal content, respectively, for supplying signals to said data output means; control means responsive to said data output means to simultaneously decrement all counters; and means in said control means jointly responsive to said control means and to respective ones of said input means to inhibit changing the count state of the respective ones of said counters.

Claim 22

Deskewing buffer circuits including in combination: a given plurality of shift registers each having a first plurality of shift stages, each stage having a shift register output means, one of said stages in each shift register being an input stage for such shift register; said given plurality of counters respectively operatively connected to said shift registers, one counter per shift register and each said counter selectively supplying an actuating signal to one of said register output means in the respective shift register in accordance with the signal content of said each counter; said given plurality of input means supplying control signals to said counters and shift registers, respectively, for simultaneously actuating said counters to increment by one and said shift register to shift its signal contents by one stage toward one end of each said respective shift registers, data means in said input means simultaneously supplying data signals to said shift registers for storing same in said shift registers, respectively; data output means for simultaneously receiving signals from any one stage in all said shift registers, said shift register output means in each said shift registers responsive to the signal content of the respective said counters to select said any one stage in accordance with the counter signal content, respectively, for supplying signals to said data output means; control means responsive to said data output means to simultaneously decrement all counters; and means in said control means jointly responsive to said control means and to respective ones of said input means to inhibit changing the count state of the respective ones of said counters.

Claim 23

A data signal shift register buffer having a given number of shift stages, means for shifting the data signal content one stage at a time from a first end one shift stage toward a second end one shift stage, input data means, output data means, the improvement including in combination: scanning means electrically interposed between one of said data means and said register for exchanging data signals between said one data means and any one of said shift stages, transfer means electrically interposed between one of said end one shift stages and a data means other than said one data means for exchanging data signals therebetween; an up/down counter having said given number, plus one, of count states and corresponding count indicating lines, said count indicating lines being connected to said scanning means, said scanning means responsive to said stable count indicating states to transfer data signals between one of said shift stages corresponding to said shift states and said one data means said count state representing said given number, plus one, not having one of said corresponding lines, and control means responsive to said transferring means transferring a data signal to alter the stable count state of said up/down counter and including inhibit means jointly responsive to said scanning means and said transferring means, each transferring a data signal to inhibit said control means, and shift control means in said control means responsive to said transferring means to actuate said shift register to shift the data signal content one stage.

Claim 24

A data signal shift register buffer having a given number of shift stages, means for shifting the data signal content one stage at a time from a first end one shift stage toward a second end one shift stage, input data means, output data means, the improvement including in combination: scanning means electrically interposed between one of said data means and said register for exchanging data signals between said one data means and any one of said shift stages, transfer means electrically interposed between one of said end one shift stages and a data means other than said one data means for exchanging data signals therebetween; an up/down counter having said given number, plus one, of count states and corresponding count indicating lines, said count indicating lines being connected to said scanning means, said scanning means responsive to said stable count indicating states to transfer data signals between one of said shift stages corresponding to said shift states and said one data means said count state representing said given number, plus one, not having one of said corresponding lines, and control means responsive to said transferring means transferring a data signal to alter the stable count state of said up/down counter and including inhibit means jointly responsive to said scanning means and said transferring means, each transferring a data signal to inhibit said control means, and shift control means in said control means responsive to said transferring means to actuate said shift register to shift the data signal content one stage.

Claim 27

The method set forth in claim 21 further including the steps of: designating one shift stage in each shift register as an input stage for receiving all data signals to be inserted and designating one shift stage in each shift register by a present count state in its associated up/down counter as an output stage.

Claim 28

The method set forth in claim 21 further including the steps of: designating a shift stage in each shift register in said one data exchange based upon the present count state in each said up/down counter; designating one shift stage in each shift register as a shift stage in each shift register for said another one of said data exchanges; and repeatedly designating said one shift stage for said one data exchange in at least one of said shift registers.

Claim 29

The method set forth in claim 23 further including the steps of: analyzing the count states in said up/down counters; and when any one up/down counter reaches a predetermined count, supplying an indicating signal signifying a given deskewing status.

Claim 32

Shift register apparatus for effecting data signal exchanges between data input means, data output means and a shift register having a given number of shift stages, means interconnecting said shift stages for shifting signal content one stage at a time from a first end one shift stage toward a second end one shift stage thereof in response to a shift control signal, the improvement including in combination: an up/down counter having said given number, plus one, of stable signal state lines; means connecting all but said plus-one of said stable signal state lines to said shift stages, respEctively, each of said lines connected to only one of said shift stages; data control means supplying said shift control pulse in response to said data signal exchanges; and common counter control means in said counter jointly responsive to said data signal exchanges and said shift control pulse to selectively alter said up/down counter stable states in accordance therewith.

Claim 33

Shift register apparatus for effecting data signal exchanges between data input means, data output means and a shift register having a given number of shift stages, means interconnecting said shift stages for shifting signal content one stage at a time from a first end one shift stage toward a second end one shift stage thereof in response to a shift control signal, the improvement including in combination: an up/down counter having said given number, plus one, of stable signal state lines; means connecting all but said plus-one of said stable signal state lines to said shift stages, respEctively, each of said lines connected to only one of said shift stages; data control means supplying said shift control pulse in response to said data signal exchanges; and common counter control means in said counter jointly responsive to said data signal exchanges and said shift control pulse to selectively alter said up/down counter stable states in accordance therewith.

Claim 34

The shift register apparatus set forth in claim 26 further including in combination: output control means in said data control means responsive to said plus-one state to inhibit any data exchanges which include taking data signals out of said shift register.

Claim 35

The shift register apparatus of claim 26 further including input control means in said data control means responsive to a predetermined count state of said up/down counter to inhibit data exchanges which include inserting data signals into said shift register.

Claim 36

The shift register apparatus set forth in claim 26 wherein said data control means further includes in combination: input data control means capable of receiving data input signals for insertion into said shift register and inserting said received data signals into said shift register irrespective of the count state of said up/down counter; output data control means having independent timing request means and operative to take data signals from said shift register in accordance with said independent timing means irrespective of the count state of said up/down counter; and mode control means selecting one of said data control means to control operation of said shift register.

Claim 37

The shift register apparatus set forth in claim 29 further including in combination: error means monitoring said up/down counter and responsive to said mode control means and to predetermined ones of said stable count states to signify an overrun or underrun type of error in accordance with said mode control means selection.