Reversible rate multiplier

Claim 2

A bidirectional digital Rate multiplier comprising: up/down binary counting means for counting a train of count pulses and having a plurality of binary stages each having a non-carry output circuit, said output circuits providing non-carry transitions which are mutually exclusive in time during a counting interval and are of a direction dependent upon the counting direction of said counting means; counter control means for selectively conditioning said counting means to count said received count pulses in an up direction or in a down direction; logic circuit means connected to said non-carry output circuits for sensing said transitions of said plurality of said stages and including direction sensing means for detecting the direction of each of said sensed transitions; and, output circuit means providing a plurality of output pulses corresponding with the number of said sensed and direction detected transitions.

Claim 3

A bidirectional digital rate multiplier as set forth in claim 1, wherein said output circuit means includes gating means controlled by said direction sensing means to provide said output pulses.

Claim 4

A bidirectional digital rate multiplier as set forth in claim 1, wherein said direction sensing means respectively provides a first pulse and a second pulse each time a said sensed transition is in a first direction or a second direction.

Claim 5

A bidirectional digital rate multiplier as set forth in claim 3, wherein said output circuit means includes first and second gate means respectively responsive to said first and second pulses from said direction sensing means to correspondingly provide said plurality of output pulses.

Claim 6

A bidirectional digital rate multiplier as set forth in claim 4, wherein each of said first and second gate means has an output circuit so that the output circuit for said first gate means carries output pulses corresponding to and in number with said transitions in the first direction and the output circuit for said second gate means carries output pulses corresponding to and in number to said transitions in the second direction.

Claim 7

A bidirectional digital multiplier as set forth in claim 1, wherein said logic circuit means include a plurality of pulse gating means respectively connected to the output circuits of said plurality of binary counting stages, means for selectively enabling said plurality of pulse gating means so that each enabled gating means provides an output pulse corresponding to each non-carry transition on the output circuit of its associated counting stage.

Claim 8

A bidirectional digital rate multiplier as set forth in claim 6 including differentiating means connected to each of said gating means for providing an output pulse each time the associated gating means provides an output pulse representative of a non-carry transition in a first direction.

Claim 9

A bidirectional digital rate multiplier as set forth in claim 7 including a second differentiating circuit connected to each said gating means for providing an output pulse each time its said associated pulse gating means provides an output pulse representative of a non-carry transition in a second direction.

Claim 10

A bidirectional digital rate multiplier comprising: up/down binary counting means for counting a train of count pulses and having a plurality of binary stages each having an output circuit, said output circuits providing non-carry transitions which are mutually exclusive in time during a counting interval and are of a direction dependent upon the counting direction of said counting means; counter control means for selectively conditioning said counting means to count said received count pulses in an up direction or in a down direction; logic circuit means for sensing said transitions of at least one of said stages and including direction sensing means for detecting the direction of each of said sensed transitions, a plurality of pulse gating means respectively connected to the output circuits of said plurality of binary counting stages, means for selectively enAbling said plurality of pulse gating means so that each enabled gating means provides an output pulse corresponding to each non-carry transition on the output circuit of its associated counting stage, first differentiating means connected to each of said gating means for providing an output pulse each time the associated gating means provides an output pulse representative of a non-carry transition in a first direction, second differentiating means connected to each said gating means for providing an output pulse each time its said associated pulse gating means provides an output pulse representative of a non-carry transition in a second direction, first and second pulse gating means each having a plurality of input circuits with the input circuits of said first output gating means being connected to the respective said first differentiating means associated with said plurality of pulse gating means and said second output gating means having a plurality of input circuits respectively connected to said respective second differentiating circuit means associated with said plurality of gating means, whereby said first and second output gating means provide first and second output pulse trains respectively including a number of output pulses corresponding in number to the number of pulses provided by the said respectively associated differentiating means, and output circuit means providing a plurality of output pulses corresponding with the number of said sensed and direction detected transitions.

Claim 11

A bidirectional digital rate multiplier comprising: up/down binary counting means for counting a train of count pulses and having a plurality of binary stages each having an output circuit, said output circuits providing non-carry transitions which are mutually exclusive in time during a counting interval and are of a direction dependent upon the counting direction of said counting means; counter control means for selectively conditioning said counting means to count said received count pulses in an up direction or in a down direction; logic circuit means for sensing said transitions of at least one of said stages and including direction sensing means for detecting the direction of each of said sensed transitions, a plurality of pulse gating means respectively connected to the output circuits of said plurality of binary counting stages, means for selectively enAbling said plurality of pulse gating means so that each enabled gating means provides an output pulse corresponding to each non-carry transition on the output circuit of its associated counting stage, first differentiating means connected to each of said gating means for providing an output pulse each time the associated gating means provides an output pulse representative of a non-carry transition in a first direction, second differentiating means connected to each said gating means for providing an output pulse each time its said associated pulse gating means provides an output pulse representative of a non-carry transition in a second direction, first and second pulse gating means each having a plurality of input circuits with the input circuits of said first output gating means being connected to the respective said first differentiating means associated with said plurality of pulse gating means and said second output gating means having a plurality of input circuits respectively connected to said respective second differentiating circuit means associated with said plurality of gating means, whereby said first and second output gating means provide first and second output pulse trains respectively including a number of output pulses corresponding in number to the number of pulses provided by the said respectively associated differentiating means, and output circuit means providing a plurality of output pulses corresponding with the number of said sensed and direction detected transitions.

Claim 12

A bidirectional digital rate multiplier as set forth in claim 9 including pulse inverting means interposed between each of said second differentiating means and the output circuits of said respectively associated pulse gating means.

Claim 13

A bidirectional digital rate multiplier as set forth in claim 1 wherein said counter control means includes direction logic circuit means for receiving two identical but phase displaced trains of input count pulses from a bidirectional pulse source and means for comparing said pulse trains to determine whether said pulse trains are in a forward direction or a reverse direction and providing an output signal exhibiting a characteristic in dependence upon the determined direction.

Claim 14

A bidirectional digital rate multiplier comprising: up/down binary counting means for counting a train of count pulses and having a plurality of binary counting stages each having a non-carry output circuit, each said output circuit carrying a binary signal of a binary level representative of the binary state of its associated counting stage during the counting operations; counter control means for selectively controlling said counting means to count said count pulses in an up direction or in a down direction; logic circuit means connected to said non-carry output circuits for monitoring the binary states of selected ones of said stages during the counting operation and providing a gate enabling signal each time the monitored stages exhibit preselected binary levels, output pulse gating means for receiving a train of pulses corresponding with said input train of count pulses and enabled by each said enabling signal to provide an output pulse so that during the counting interval the total number of output pulses correspond with the number of times said output gating means is enabled during the counting interval.

Claim 15

A bidirectional digital rate multiplier comprising: up/down binary counting means for counting a train of count pulses and having a plurality of binary counting stages each having a non-carry output circuit, each said output circuit carrying a binary signal of a binary level representative of the binary state of its associated counting stage during the counting operations; counter control means for selectively controlling said counting means to count said count pulses in an up direction or in a down direction; logic circuit means connected to said non-carry output circuits for monitoring the binary states of selected ones of said stages during the counting operation and providing a gate enabling signal each time the monitored stages exhibit preselected binary levels, output pulse gating means for receiving a train of pulses corresponding with said input train of count pulses and enabled by each said enabling signal to provide an output pulse so that during the counting interval the total number of output pulses correspond with the number of times said output gating means is enabled during the counting interval.

Claim 16

A bidirectional digital rate multiplier as set forth in claim 12 including means for inhibiting said output pulse gating means from being enabled by a said enabling pulse and thereby prevent passage of an associated output pulse each time the binary counting means is conditioned to reverse its direction of counting.

Claim 17

A bidirectional digital rate multiplier as set forth in claim 12 wherein said logic circuit means includes a plurality of gating means connected to different combinations of said binary counter output circuits so that each gating means provides a said enabling pulse each time an associated combination of said stages Exhibit a particular pattern of binary states.

Claim 18

A bidirectional digital rate multiplier as set forth in claim 14 including selectively actuatable switching means for selectively connecting the output circuits of said gating means with said pulse gating means to vary the number of output pulses provided by said pulse gating means.

Claim 19

A bidirectional digital rate multiplier as set forth in claim 12 wherein said counter control means includes a direction logic circuit for receiving two trains of phase displaced count pulses and providing an output manifestation indicative of whether the pulse trains are representative of a forward direction or a backward direction, said direction logic circuit including means for monitoring one of said pulse trains for a particular binary level and sensing the direction of pulse transition of the corresponding pulse in the other pulse train to determine the direction of said pulse trains.

Claim 20

A bidirectional rate multiplier comprising: up/down binary counting means for counting a train of count pulses and having a plurality of cascaded binary counting stages each having a non-carry output circuit, said output circuits providing non-carry transitions which are mutually exclusive in time during a counting interval and are of a direction dependent upon the counting direction of said counting means; counter control means for selectively conditioning said counting means to count said received count pulses in an up direction or in a down direction; logic circuit means connected to said non-carry output circuits for sensing the binary state of selected ones of said binary stages during the counting operation and providing a gate enabling signal each time said selected stage or stages exhibits a given binary state; pulse gating means enabled by each said gate enabling signal to pass an input count pulse; and, output circuit means providing a train of said passed count pulses corresponding in number with the number of times said gating means is enabled during a said counting interval.

Claim 21

A bidirectional rate multiplier comprising: up/down binary counting means for counting a train of count pulses and having a plurality of cascaded binary counting stages each having a non-carry output circuit, said output circuits providing non-carry transitions which are mutually exclusive in time during a counting interval and are of a direction dependent upon the counting direction of said counting means; counter control means for selectively conditioning said counting means to count said received count pulses in an up direction or in a down direction; logic circuit means connected to said non-carry output circuits for sensing the binary state of selected ones of said binary stages during the counting operation and providing a gate enabling signal each time said selected stage or stages exhibits a given binary state; pulse gating means enabled by each said gate enabling signal to pass an input count pulse; and, output circuit means providing a train of said passed count pulses corresponding in number with the number of times said gating means is enabled during a said counting interval.