Skew correction buffer

Claim 1

A SKEW CORRECTING CIRCUIT COMPRISING: (A) ONLY ONE INFORMATION CHANNEL MEANS FOR RECEIVING A FIRST SINGLE SERIAL TRAIN OF BITS BELONGING TO A PLURALITY OF Z START PATTERN FRAMES AND Y DATA FRAMES, AND A SPROKET CHANNEL MEANS FOR RECEIVING SECOND SIGNAL SERIAL TRAIN OF SPROCKET BITS ONE FOR EACH OF SAID START PATTERN BITS AND DATA BITS, WHERE EACH ZTH START PATTERN FRAME AND YTH DATA FRAME IS COMPRISED OF A SERIAL GROUP OF N ORDERED BITS EACH NTH ORGER BIT OF WHICH IS SERIALLY FED ALONG SAID ONE INFORMATION CHANNEL MEANS AND WHICH, TOGETHER WITH IS SPROCKET BIT, SIMULTANEOUSLY APPEAR DURING A CORRESPONDING NTH TIME INTERVAL OF SOME ONE OF A GROUP OF SUCCESSIVE MACHINE CYCLES EACH CYCLE CONSISTING OF N SUCCESSIVE TIME INTERVALS, WITH DIFFERENT NTH ORDER BITS OF THE SAMD ZTH START PATTERN FRAME OR YTH DATA FRAME APPEARING DURING THE SAME OR DIFFERENT MACHINE CYCLES DEPENDING UPON THE AMOUNT OF SKEW, AND WHERE ALL CORRESPONDING NTH ORDER BITS OF ALL Z START PATTERN FRAMES APPEAR PRIOR TO THE APPEARANCE OF THE CORRESPONDING NTH ORGER BIRTS OF ANY DATA FRAME, WITH ANY NTH ORDER BIT OF A RESPECTIVE ZTH START PATTERN FRAME AND YTH DATA FRAME APPEARING PRIOR TO THE APPEARANCE OF THE CORRESPONDING NTH ORDER BIT OF THE Z+1TH START PATTERN FRAME AND THE Y+1TH DATA FRAME, RESPECTIVELY; (B) A GROUP OF M FRAME REGISTERS EACH CONNECTED WITH SAID ONE INFORMATION CHANNEL MEANS AND EACH COMPRISED OF A N BIT DYNAMIC RECIRCULATING LOOP WITH A ONE MACHINE CYCLE TIME DELAY BETWEEN ITS INPUT AND OUTPUT; (C) A CONTROL REGISTER COMPRISED OF N BIT DYNAMIC RECIRCULATING LOOP WITH A ONE MACHINE CYCLE TIME DELAY BETWEEN ITS INPUT AND OUTPUT; (D) FIRST SENSING MEANS CONNECTED WITH SAID SPROCKET CHANNEL MEANS AND RESPONSIVE DURING ANY NTH TIME INTERVAL TO A FIRST PREDETERMINED BIT VALUE APPEARING FROM THE OUTPUT OF SAID CONTROL REGISTER AND TO AN APPEARING SPROCKET BIT FOR INHIBITING THE RECIRCULATION OF EACH SAID FRAME REGISTER AND INSTEAD APPLYING A THEN APPEARING NTH ORDER START PATTERN BIT TO THE INPUT OF THE MTH FRAME REGISTER WHILE TRANFERRING THE OUTPUT OF EACH MTH FRAME REGISTER TO THE INPUT OF THE M-1TH FRAME REGISTER; (E) SECOND SENSING MEANS CONNECTED WITH SAID SPROCKET CHANNEL MEANS AND RESPONSIVE DURING ANY NTH TIME INTERVAL TO A SAID FIRST PREDETERMINED BIT VALUE APPEARING FROM THE OUTPUT OF SAID CONTROL REGISTER, TO AN APPEARING SPROCKET BIT TO THE THEN APPEARING START PATTERN BIT AND TO THE OCCURRENCE OF A PARTICULAR START PATTERN BIT CODE CONFIGURATION AT THE OUTPUTS OF ALL OF SAID FRAME REGISTERS FOR APPLYING SAID FIRST PREDETERMINED BIT VALUE TO THE INPUT OF THE M=1 FRAME REGISTER, AND APPLYING THE OPPOSITE BIT VALUE TO THE INPUT OF THE M=2 FRAME REGISTER AND TO THE INPUT OF SAID CONTROL REGISTER; (F) THIRD SENSING MEANS ENABLED DURING ANY NTH TIME INTERVAL TO SAID OPPOSITE BIT VALUE APPEARING FROM THE OUTPUT OF SAID CONTROL REGISTER, TO THE OCCURRENCE OF SAID FIRST PREDETERMINED BIT VALUE AT THE OUTPUT OF ANY MTH FRAME REGISTER, AND TO THE OCCURRENCE OF SAID OPPOSITE BIT VALUE AT THE OUTPUT OF EACH OF THE M+1TH THROUGH THE MTH FRAME REGISTERS THEREBY TO INHIBIT THE RECIRCULATION OF SAID MTH AND M+1TH FRAME REGISTERS DURING A SAID LAST NAMED TIME INTERVAL AND INSTEAD TO APPLY A THEN APPEARING NTH ORDER DATA TO THE INPUT OF SAID MTH FRAME REGISTER AND TO APPLY SAID FIRST PREDETERMINED BIT VALUE TO THE INPUT OF SAID M+1TH FRAME REGISTER.