US5268937A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and system for digital transmission of serial data
Assignee: Bull SAS
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Filing: 1991-07-09
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Granted: 1993-12-07
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Expires: 2011-07-09
Abstract
Abstract The digital data transmission is of the type including the addition of clock and synchronizing information to the data to constitute the transmission signal, and the determination of the transmission speed from this received information. According to the invention, this information, in the transmission signal, comprises a synchronizing edge (SYNC) added to each group of N data bits (D0-D7, OP), and the determination of the transmission speed comprises producing N clock signals (CL0-CL9) from identical successive delays (480-489) of a synchronizing edge detected.
Inventors
- 👤 Roland Marbot
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 02:05
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337; H04L7/04; H04L7/048
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
76 words
A method of digital transmission of a serial transmission signal, comprising the steps of successively and serially producing a signal group including a synchronizing edge and N data bits to form the serial transmission signal, wherein said synchronizing edge includes clock information and synchronizing information, detecting said synchronizing edge from said signal group and generating a predetermined number of equally spaced and successively delayed clock signals therefrom to determine the transmission speed of the transmission signal.
Claim 2
Independent Claim
76 words
A method of digital transmission of a serial transmission signal, comprising the steps of successively and serially producing a signal group including a synchronizing edge and N data bits to form the serial transmission signal, wherein said synchronizing edge includes clock information and synchronizing information, detecting said synchronizing edge from said signal group and generating a predetermined number of equally spaced and successively delayed clock signals therefrom to determine the transmission speed of the transmission signal.
Claim 3
Dependent Claim
26 words
The method of claim 1, wherein the step of producing said signal group further includes producing at least one synchronizing bit to form said synchronizing edge.
Claim 4
Dependent Claim
34 words
The method of claim 1, wherein said N data bits include an parity/odd parity bit (OP) and the step of producing said signal group further includes the step of referencing said parity/odd parity bit.
Claim 5
Dependent Claim
34 words
The method of claim 2, wherein said N data bits include an parity/odd parity bit (OP) and the step of producing said signal group further includes the step of referencing said parity/odd parity bit.
Claim 6
Dependent Claim
47 words
The method of claim 1, wherein the step of producing a signal group includes producing at least one successive pair of signal group, and the step of detecting said synchronizing edge includes detecting only one synchronizing edge from said at least one successive pair of signal groups.
Claim 7
Dependent Claim
47 words
The method of claim 2, wherein the step of producing a signal group includes producing at least one successive pair of signal groups, and the step of detecting said synchronizing edge includes detecting only one synchronizing edge from said at least one successive pair of signal groups.
Claim 8
Dependent Claim
47 words
The method of claim 3, wherein the step of producing a signal group includes producing at least one successive pair of signal groups, and the step of detecting said synchronizing edge includes detecting only one synchronizing edge from said at least one successive pair of signal groups.
Claim 9
Independent Claim
94 words
A system for digital data transmission, comprising transmitting means for successively and serially producing a signal group including a synchronizing edge and N data bits to form a serial transmission signal, wherein said synchronizing edge includes clock information and synchronizing information, and means for receiving said serial transmission signal, said receiving means including means for detecting said synchronizing edge from said signal group and means for generating from the detected synchronizing edge a predetermined number of equally and successively delayed clock signals which enable the transmission speed of said transmission signal to be determined.
Claim 10
Independent Claim
94 words
A system for digital data transmission, comprising transmitting means for successively and serially producing a signal group including a synchronizing edge and N data bits to form a serial transmission signal, wherein said synchronizing edge includes clock information and synchronizing information, and means for receiving said serial transmission signal, said receiving means including means for detecting said synchronizing edge from said signal group and means for generating from the detected synchronizing edge a predetermined number of equally and successively delayed clock signals which enable the transmission speed of said transmission signal to be determined.
Claim 11
Dependent Claim
21 words
The system of claim 8, wherein said transmitting means includes a delay device having a plurality of identical series-connected delay elements.
Claim 12
Dependent Claim
20 words
The system of claim 9, wherein the transmitting means includes a phase lock loop which incorporates said delay device therein.
Claim 13
Dependent Claim
37 words
The system of claim 8, wherein said means for detecting said synchronizing edge includes at least one edge register having a clock input, said edge register being operable to receive said transmission signal at said clock input.
Claim 14
Dependent Claim
39 words
The system of claim 8, wherein said means for receiving said serial transmission signal includes a clock recuperator connected to receive said clock information, said recuperator having a validation circuit for validating said transmission signal at said edge register.
Claim 15
Dependent Claim
23 words
The system of claim 12, wherein said validation circuit includes a delay circuit for producing a delay with respect to said synchronizing edge.
Claim 16
Dependent Claim
25 words
The system of claim 13, wherein said delay produced by said delay circuit is adjusted to a predetermined value with respect to said synchronizing edge.
Claim 17
Dependent Claim
42 words
The system of claim 8, wherein said transmission means is operable to produce at least one successive pair of signal groups, and said detector means is operable to detect only one synchronizing edge from said at least one pair of signal groups.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-06 | 1997-06-07 | 1997-12-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-06 | 2001-06-07 | 2001-12-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-06 | 2005-06-07 | 2005-12-07 | $7700.00 | Window Closed / Lapsed |