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US6255232B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Method for forming low dielectric constant spin-on-polymer (SOP) dielectric layer

Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1999-02-11
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Granted: 2001-07-03
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Expires: 2019-02-11
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Abstract

Abstract A method for forming a dielectric layer upon a substrate within a microelectronics fabrication. There is provided a substrate. There is then formed upon the substrate while employing a low dielectric constant spin-on material a dielectric layer which is subsequently cured at atmospheric pressure at an elevated temperature to stabilize the physical and chemical properties of the low dielectric constant dielectric layer so as to attenuate shrinkage and other changes in those physical, and chemical properties from thermal annealing at sub-atmospheric pressure due to typical further microelectronics fabrication processing steps.

Inventors

  • 👤 Weng Chang
  • 👤 Yao-Yi Cheng
  • 👤 Syun-Ming Jang

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 19:40
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/68; H10P14/683; H10P14/687; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6342; H10P14/66; H10P14/665; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 172 words
A method for forming a dielectric layer upon a substrate employed within a microelectronics fabrication comprising: providing a substrate; forming over the substrate a dielectric layer formed of a spin-on-polymer (SOP) dielectric material, the spin-on-polymer (SOP) dielectric material being susceptible to greater shrinkage when thermally processed at sub-atmospheric pressure than when thermally processed at atmospheric pressure; the SOP dielectric material comprised of a material selected from the group comprising poly (arylene ether) and fluorinated poly (arylene ether); thermally processing the dielectric layer at atmospheric pressure to form an atmospheric pressure thermally processed dielectric layer with attenuated shrinkage in comparison with a sub-atmospheric pressure thermally processed dielectric layer; the thermal processing being conducted at a temperature from about 350 to 450° C. for from about 10 to 120 minutes; and thermally processing the atmospheric pressure thermally processed dielectric layer at a sub-atmospheric pressure to form a sub-atmospheric pressure thermally processed atmospheric pressure thermally processed dielectric layer with attenuated shrinkage in comparison with an atmospheric pressure thermally processed sub-atmospheric pressure thermally processed dielectric layer.
Claim 2
Independent Claim 172 words
A method for forming a dielectric layer upon a substrate employed within a microelectronics fabrication comprising: providing a substrate; forming over the substrate a dielectric layer formed of a spin-on-polymer (SOP) dielectric material, the spin-on-polymer (SOP) dielectric material being susceptible to greater shrinkage when thermally processed at sub-atmospheric pressure than when thermally processed at atmospheric pressure; the SOP dielectric material comprised of a material selected from the group comprising poly (arylene ether) and fluorinated poly (arylene ether); thermally processing the dielectric layer at atmospheric pressure to form an atmospheric pressure thermally processed dielectric layer with attenuated shrinkage in comparison with a sub-atmospheric pressure thermally processed dielectric layer; the thermal processing being conducted at a temperature from about 350 to 450° C. for from about 10 to 120 minutes; and thermally processing the atmospheric pressure thermally processed dielectric layer at a sub-atmospheric pressure to form a sub-atmospheric pressure thermally processed atmospheric pressure thermally processed dielectric layer with attenuated shrinkage in comparison with an atmospheric pressure thermally processed sub-atmospheric pressure thermally processed dielectric layer.
Claim 3
Dependent Claim 44 words
The method of claim 1 wherein the dielectric layer is formed upon a microelectronics fabrication chosen from the group consisting of: integrated circuit microelectronics fabrications; charge coupled device microelectronics fabrications; solar cell microelectronics fabrications; ceramic substrate microelectronics fabrications; and flat panel display microelectronics fabrications.
Claim 4
Independent Claim 95 words
A method for forming within an integrated circuit microelectronics fabrication a dielectric layer comprising: providing a semiconductor substrate; forming over the semiconductor substrate a patterned microelectronics layer; forming upon the patterned microelectronics layer a dielectric layer employing a poly (arylene ether) spin-on material; and thermally annealing the dielectric layer at a temperature from about 350 to 450° C. for from about 10 to 120 minutes at atmospheric pressure to stabilize the physical and chemical properties of the low dielectric constant dielectric layer so as to attenuate shrinkage due to further thermal annealing at sub-atmospheric pressure.
Claim 5
Independent Claim 95 words
A method for forming within an integrated circuit microelectronics fabrication a dielectric layer comprising: providing a semiconductor substrate; forming over the semiconductor substrate a patterned microelectronics layer; forming upon the patterned microelectronics layer a dielectric layer employing a poly (arylene ether) spin-on material; and thermally annealing the dielectric layer at a temperature from about 350 to 450° C. for from about 10 to 120 minutes at atmospheric pressure to stabilize the physical and chemical properties of the low dielectric constant dielectric layer so as to attenuate shrinkage due to further thermal annealing at sub-atmospheric pressure.
Claim 6
Dependent Claim 14 words
The method of claim 3 wherein the semiconductor substrate is a silicon semiconductor substrate.
Claim 7
Dependent Claim 15 words
The method of claim 3 wherein the patterned microelectronics layer is a patterned conductor layer.
Claim 8
Dependent Claim 118 words
The method of claim 1 , wherein the sub-atmospheric pressure thermally processed atmospheric pressure thermally processed poly (arylene ether) dielectric layer having a shrinkage of about 2.00%, and about a 2.7% decrease in change in line-line capacitance and about a 5.31% decrease in stress variation compared to an atmospheric pressure thermally processed sub-atmospheric pressure thermally processed poly (arylene ether) dielectric layer; and the sub-atmospheric pressure thermally processed atmospheric pressure thermally processed fluorinated poly (arylene ether) dielectric layer having a shrinkage of about 8.80%, and about a 6.1% decrease in change in line-line capacitance and about a 4.29% decrease in stress variation compared to an atmospheric pressure thermally processed sub-atmospheric pressure thermally processed fluorinated poly (arylene ether) dielectric layer.
Claim 9
Dependent Claim 61 words
The method of claim 3 , wherein the sub-atmospheric pressure thermally processed atmospheric pressure thermally processed poly (arylene ether) dielectric layer having a shrinkage of about 2.00%, and about a 2.7% decrease in change in line-line capacitance and about a 5.31% decrease in stress variation compared to an atmospheric pressure thermally processed sub-atmospheric pressure thermally processed poly (arylene ether) dielectric layer.
Claim 10
Independent Claim 282 words
A method for forming a dielectric layer upon a substrate employed within a microelectronics fabrication comprising: providing a substrate; p 1 forming over the substrate a dielectric layer formed of a spin-on-polymer (SOP) dielectric material, the spin-on-polymer (SOP) dielectric material being susceptible to greater shrinkage when thermally processed at sub-atmospheric pressure than when thermally processed at atmospheric pressure; the SOP comprised of a material selected from the group comprising poly (arylene ether) and fluorinated poly (arylene ether); thermally processing the dielectric layer at atmospheric pressure to form an atmospheric pressure thermally processed dielectric layer with attenuated shrinkage in comparison with a sub-atmospheric pressure thermally processed dielectric layer; the thermal processing being conducted at a temperature from about 350 to 450° C. for from about 10 to 120 minutes; and thermally processing the atmospheric pressure thermally processed dielectric layer at a sub-atmospheric pressure to form a sub-atmospheric pressure thermally processed atmospheric pressure thermally processed dielectric layer with attenuated shrinkage in comparison with an atmospheric pressure thermally processed sub-atmospheric pressure thermally processed dielectric layer; the sub-atmospheric pressure thermally processed atmospheric pressure thermally processed poly (arylene ether) dielectric layer having a shrinkage of about 2.00%, and about a 2.7% decrease in change in line-line capacitance and about a 5.31% decrease in stress variation compared to an atmospheric pressure thermally processed sub-atmospheric pressure thermally processed poly (arylene ether) dielectric layer; the sub-atmospheric pressure thermally processed atmospheric pressure thermally processed fluorinated poly (arylene ether) dielectric layer having a shrinkage of about 8.80%, and about a 6.1% decrease in change in line-line capacitance and about a 4.29% decrease in stress variation compared to an atmospheric pressure thermally processed sub-atmospheric pressure thermally processed fluorinated poly (arylene ether) dielectric layer.
Claim 11
Independent Claim 282 words
A method for forming a dielectric layer upon a substrate employed within a microelectronics fabrication comprising: providing a substrate; p 1 forming over the substrate a dielectric layer formed of a spin-on-polymer (SOP) dielectric material, the spin-on-polymer (SOP) dielectric material being susceptible to greater shrinkage when thermally processed at sub-atmospheric pressure than when thermally processed at atmospheric pressure; the SOP comprised of a material selected from the group comprising poly (arylene ether) and fluorinated poly (arylene ether); thermally processing the dielectric layer at atmospheric pressure to form an atmospheric pressure thermally processed dielectric layer with attenuated shrinkage in comparison with a sub-atmospheric pressure thermally processed dielectric layer; the thermal processing being conducted at a temperature from about 350 to 450° C. for from about 10 to 120 minutes; and thermally processing the atmospheric pressure thermally processed dielectric layer at a sub-atmospheric pressure to form a sub-atmospheric pressure thermally processed atmospheric pressure thermally processed dielectric layer with attenuated shrinkage in comparison with an atmospheric pressure thermally processed sub-atmospheric pressure thermally processed dielectric layer; the sub-atmospheric pressure thermally processed atmospheric pressure thermally processed poly (arylene ether) dielectric layer having a shrinkage of about 2.00%, and about a 2.7% decrease in change in line-line capacitance and about a 5.31% decrease in stress variation compared to an atmospheric pressure thermally processed sub-atmospheric pressure thermally processed poly (arylene ether) dielectric layer; the sub-atmospheric pressure thermally processed atmospheric pressure thermally processed fluorinated poly (arylene ether) dielectric layer having a shrinkage of about 8.80%, and about a 6.1% decrease in change in line-line capacitance and about a 4.29% decrease in stress variation compared to an atmospheric pressure thermally processed sub-atmospheric pressure thermally processed fluorinated poly (arylene ether) dielectric layer.
Claim 12
Dependent Claim 44 words
The method of claim 13 wherein the dielectric layer is formed upon a microelectronics fabrication chosen from the group consisting of: integrated circuit microelectronics fabrications, charge coupled device microelectronics fabrications, solar cell microelectronics fabrications, ceramic substrate microelectronics fabrications, and flat panel display microelectronics fabrications.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-07-02 2005-01-01 2005-07-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-07-02 2009-01-01 2009-07-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-07-02 2013-01-01 2013-07-03 $7700.00 Window Closed / Lapsed

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