US6124164A
Expired / Lapsed
US
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Method of making integrated capacitor incorporating high K dielectric
Assignee: Micron Technology Inc
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Filing: 1998-09-17
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Granted: 2000-09-26
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Expires: 2018-09-17
Abstract
Abstract An integrated capacitor is provided, incorporating a high dielectric constant material. In a disclosed method, a high k capacitor dielectric is formed in the shape of a container above a protective layer. After the dielectric is formed, inner and outer electrodes are formed, representing storage and reference electrodes of a memory cell. Contact is separately made through the protective layer from a storage electrode layer, which lines the inner surface of the dielectric, to an underlying polysilicon plug. The contact can be a thin layer lining the interior of the storage electrode layer, or can completely fill the container capacitor. In the latter instance, the contact can form part of the storage electrode and contribute to capacitance of the cell. Volatile dielectric materials can thus be formed prior to the electrodes, avoiding oxidation of the electrodes and underlying polysilicon plug, while also minimizing oxygen depletion through diffusion from the high dielectric constant material.
Inventors
- 👤 Husam N. Al-Shareef
- 👤 Er-Xuan Ping
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 16:52
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/682; H10D1/01; H10D1/041; H10D1/042; H10D1/692; H10D1/711; H10D1/716; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
61 words
A process for forming a capacitor in an integrated circuit, comprising: forming an insulative protective layer above a circuit node; forming a dielectric layer above the protective layer; forming a first conductive layer on a first side of the dielectric layer after forming the dielectric layer; and electrically connecting the first conductive layer to the circuit node through the protective layer.
Claim 2
Dependent Claim
61 words
A process for forming a capacitor in an integrated circuit, comprising: forming an insulative protective layer above a circuit node; forming a dielectric layer above the protective layer; forming a first conductive layer on a first side of the dielectric layer after forming the dielectric layer; and electrically connecting the first conductive layer to the circuit node through the protective layer.
Claim 3
Dependent Claim
19 words
The process of claim 1, wherein the dielectric layer comprises a dielectric material characterized by a high dielectric constant.
Claim 4
Dependent Claim
19 words
The process of claim 2, wherein the dielectric material is characterized by a dielectric constant greater than about 30.
Claim 5
Dependent Claim
15 words
The process of claim 3, wherein the dielectric material is a species of complex oxide.
Claim 6
Dependent Claim
13 words
The process of claim 4, wherein the dielectric material comprises barium strontium titanate.
Claim 7
Dependent Claim
63 words
The process of claim 1, wherein electrically connecting the first conductive layer to the circuit node comprises: depositing the first conductive layer in direct contact with the dielectric layer; etching a contact via through the protective layer; and depositing a second conductive layer into the contact via, the second conductive layer directly contacting each of the first conductive layer and the circuit node.
Claim 8
Dependent Claim
26 words
The process of claim 1, further comprising forming another conductive layer on a second side of the dielectric layer, the second side opposite the first side.
Claim 9
Dependent Claim
48 words
The process of claim 7, wherein the forming the dielectric layer comprises lining a via in a structural layer above the protective layer to form a dielectric container, the first side comprising the inside of the dielectric container and the second side comprising the outside of the container.
Claim 10
Dependent Claim
15 words
The process of claim 8, further comprising filling the dielectric container with a filler material.
Claim 11
Dependent Claim
21 words
The process of claim 9, further comprising depositing a dielectric cap layer over the dielectric container after filling the dielectric container.
Claim 12
Dependent Claim
26 words
The process of claim 10, wherein the filler material comprises a conductive material and the dielectric cap layer comprises is characterized by a high dielectric constant.
Claim 13
Independent Claim
54 words
A method of forming an integrated circuit including a memory cell capacitor, comprising: forming a dielectric layer above a semiconductor substrate including a transistor active area, the dielectric layer characterized by a high dielectric constant; forming a storage electrode after forming the dielectric layer; and forming a reference electrode after forming the storage electrode.
Claim 14
Independent Claim
54 words
A method of forming an integrated circuit including a memory cell capacitor, comprising: forming a dielectric layer above a semiconductor substrate including a transistor active area, the dielectric layer characterized by a high dielectric constant; forming a storage electrode after forming the dielectric layer; and forming a reference electrode after forming the storage electrode.
Claim 15
Dependent Claim
20 words
The method of claim 12, wherein forming the storage electrode comprises lining the dielectric layer with a first conductive layer.
Claim 16
Dependent Claim
23 words
The method of claim 13, further comprising electrically connecting the first conductive layer to the transistor active area after lining the dielectric layer.
Claim 17
Dependent Claim
13 words
The method of claim 12, wherein the dielectric layer comprises a complex oxide.
Claim 18
Dependent Claim
13 words
The method of claim 15, wherein the dielectric layer comprises barium strontium titanate.
Claim 19
Dependent Claim
116 words
A process for forming a memory cell capacitor in an integrated circuit, comprising: forming an insulating protective layer above a circuit node; forming a structural layer above the protective layer; etching a via into the structural layer; lining the via with a dielectric material having a high dielectric constant to form a dielectric container; lining the dielectric container with a first conductive layer; performing a spacer etch through the dielectric container and through the protective layer to expose the circuit node; depositing a second conductive layer to electrically connect the first conductive layer to the circuit node; removing the structural layer from outside the dielectric container; and forming a third conductive layer outside the dielectric container.
Claim 20
Dependent Claim
116 words
A process for forming a memory cell capacitor in an integrated circuit, comprising: forming an insulating protective layer above a circuit node; forming a structural layer above the protective layer; etching a via into the structural layer; lining the via with a dielectric material having a high dielectric constant to form a dielectric container; lining the dielectric container with a first conductive layer; performing a spacer etch through the dielectric container and through the protective layer to expose the circuit node; depositing a second conductive layer to electrically connect the first conductive layer to the circuit node; removing the structural layer from outside the dielectric container; and forming a third conductive layer outside the dielectric container.
Claim 21
Dependent Claim
31 words
The process of claim 17, further comprising depositing an insulative cap layer over the first conductive layer, the second conductive layer and the dielectric container prior to removing the structural layer.
Claim 22
Dependent Claim
24 words
The process of claim 18, further comprising conducting a planarizing step after depositing the second conductive layer and prior to depositing the cap layer.
Claim 23
Dependent Claim
16 words
The process of claim 17, wherein depositing the second conductive layer comprises filling the dielectric container.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-09-26 | 2004-03-27 | 2004-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-09-26 | 2008-03-27 | 2008-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-09-26 | 2012-03-27 | 2012-09-26 | $7700.00 | Window Closed / Lapsed |