Stacked ferroelectric memory cell

Claim 2

A compact memory cell arrangement for an integrated circuit where the memory cell includes a ferroelectric capacitor and a transistor, and where the cell is connected to a bit line, a word line, and a plate line, the arrangement comprising: a bit line extending along a first direction, the bit line crossing over first and second source/drain regions for the transistor, and making electrical contact with said first source/drain region; a word line extending along a second direction which intersects the first direction, wherein the word line passes under the bit line; a first insulation layer covering the top of the word line where it passes through the memory cell; the plate line being constituted by a bottom electrode line extending parallel to the word line, but separated therefrom by the first insulation layer; a ferroelectric dielectric line parallel to and on top of the bottom electrode line; a top electrode contacting an upper surface of the ferroelectric line, the top electrode having a top surface and first and second spaced apart lateral edges; a local interconnect for the memory cell, extending laterally from said top surface of the top electrode along the first direction and downward to make electrical contact with the second source/drain region via a first contact window, the local interconnect and first contact window being situated beneath the bit line; the local interconnect being self-aligned to and extending from said first lateral edge of the top electrode, across the top surface thereof, and beyond said second lateral edge thereof, wherein said top surface of said top electrode is in full contact with and fully covered by said local interconnect; the plate line, ferroelectric dielectric line, and the top electrode forming a ferroelectric capacitor substantially at the intersection of the bit line and the word line, the bit line extending over said ferroelectric capacitor; wherein the plate line, ferroelectric line, bit line, and word line extend through the cell to a plurality of other memory cells.

Claim 3

The memory cell arrangement of claim 1 wherein the top electrode, ferroelectric dielectric line, and plate line are centrally located over said word line.

Claim 4

The memory cell arrangement of claim 2 wherein the plate line and ferroelectric dielectric line are wider in said first direction than said word line.

Claim 5

The memory cell arrangement of claim 1 wherein the local interconnect is insulated from the ferroelectric dielectric line by a second insulation layer.

Claim 6

The memory cell arrangement of claim 1 wherein said first insulation layer is selected from a group comprising silicon dioxide, silicon nitride, and a combination thereof.

Claim 7

The memory cell arrangement of claim 1 wherein said bottom electrode line is selected from a group comprising titanium and platinum, palladium, an alloy of platinum and palladium, and a conductive oxide.

Claim 8

The memory cell arrangement of claim 1 wherein said ferroelectric line comprises a lead zirconate titanate composition defined by a chemical composition Pb(Ti x Zr 1-x )O 3 wherein x is from 0.4 to 1.0.

Claim 9

The memory cell arrangement of claim 1 wherein said top electrode is selected from a group comprising platinum, palladium, an alloy of platinum and palladium, and a conductive oxide.

Claim 10

The memory cell arrangement of claim 1 wherein said local interconnect comprises a refractory material.

Claim 11

The memory cell arrangement of claim 9 wherein said refractory material is selected from a group comprising a refractory metal, refractory nitride, and a refractory metal silicide.

Claim 12

The memory cell arrangement of claim 9 wherein said refractory material comprises a material selected from a group comprising titanium, tungsten, tungsten-titanium alloy, molybdenum, nickel, chromium, titanium nitride, titanium silicide, zirconium nitride, hafnium nitride, tungsten silicide, molybdenum silicide, platinum silicide and cobalt silicide.

Claim 13

The memory cell arrangement of claim 1 wherein the top electrode is a local top electrode located at a discrete location above said ferroelectric dielectric line, said local top electrode being located in its corresponding memory cell only.

Claim 14

The memory cell arrangement of claim 12 wherein said top electrode and said local interconnect both have respective first lateral edges that are self-aligned with each other from having been etched together in a single etching step.

Claim 15

The memory cell arrangement of claim 13 wherein said top electrode second lateral edge is opposite and parallel to said first lateral edge; wherein said local interconnect includes a second lateral edge; wherein said second lateral edges are laterally spaced apart; and wherein said top electrode also includes third and fourth lateral edges parallel to each other and at an angle to said first and second lateral edges thereof.

Claim 16

The memory cell arrangement of claim 14 wherein said top electrode is generally centrally located over said word line.

Claim 17

The memory cell arrangement of claim 14 wherein said bottom electrode, ferroelectric layer, and top electrode are generally centrally located over the word line.

Claim 18

The memory cell arrangement of claim 1 wherein said bit line extends through an etched contact opening over the first source/drain region to make said electrical contact therewith.

Claim 19

The memory cell arrangement of claim 17 wherein said etched contact opening extends through a plurality of insulation layers.

Claim 20

The memory cell arrangement of claim 18 wherein said plurality of insulation layers includes said first insulation layer which elsewhere in the memory cell covers the top of said word line and a second insulation layer which elsewhere in the memory cell insulates the local interconnect from the ferroelectric dielectric.

Claim 21

The memory cell arrangement of claim 19 wherein said plurality of insulation layers further includes a third insulation layer which elsewhere in the memory cell insulates the local interconnect from the bit line; and wherein at said etched contact opening, said third insulation layer contacts a top of said second insulation layer, which contacts a top of said first insulation layer.

Claim 22

The memory cell arrangement of claim 1 wherein, with reference to said first direction, said bottom electrode line is as wide as said ferroelectric dielectric line, and wherein no side of said ferroelectric dielectric line in the memory cell extends beyond a side of the bottom electrode.

Claim 23

An integrated circuit array of memory cells where each memory cell includes a ferroelectric capacitor and a transistor, and where each cell is connected to a corresponding bit line, word line, and plate line, the array comprising: a plurality of bit lines, each extending along a first direction, each bit line crossing over first and second source/drain regions for at least one transistor, and making electrical contact with said first source/drain region; a plurality of word lines, each extending along a second direction, crossing under said plurality of bit lines; a first insulation layer covering the tops of said word lines in each memory cell through which the word lines pass; a plurality of plate lines, each extending parallel to a corresponding one of the word lines, but separated therefrom by the first insulation layer, each plate line forming a bottom electrode in each cell through which the plate line extends; a plurality of ferroelectric dielectric lines parallel to the plate lines, each ferroelectric line being located on top of a respective plate line; a plurality of top electrodes, each top electrode contacting an upper surface of a corresponding ferroelectric line; a plurality of local interconnects, each memory cell having a respective local interconnect in full contact with a top surface of its corresponding top electrode so that the top electrode is fully covered by the local interconnect, the local interconnect also extending laterally along the first direction and downward to make electrical contact with said second source/drain region via a first contact window, the local interconnect and first contact window being situated beneath a corresponding bit line, the local interconnect having a common lateral edge self-aligned with an edge of the corresponding top electrode; the plate lines, ferroelectric dielectric lines, and top electrodes forming a plurality of ferroelectric capacitors located substantially at each intersection of a said bit line and a said word line, the bit lines extending over the ferroelectric capacitors; wherein the plate lines, ferroelectric lines, bit lines, and word lines extend to respective pluralities of said memory cells.

Claim 24

An integrated circuit array of memory cells where each memory cell includes a ferroelectric capacitor and a transistor, and where each cell is connected to a corresponding bit line, word line, and plate line, the array comprising: a plurality of bit lines, each extending along a first direction, each bit line crossing over first and second source/drain regions for at least one transistor, and making electrical contact with said first source/drain region; a plurality of word lines, each extending along a second direction, crossing under said plurality of bit lines; a first insulation layer covering the tops of said word lines in each memory cell through which the word lines pass; a plurality of plate lines, each extending parallel to a corresponding one of the word lines, but separated therefrom by the first insulation layer, each plate line forming a bottom electrode in each cell through which the plate line extends; a plurality of ferroelectric dielectric lines parallel to the plate lines, each ferroelectric line being located on top of a respective plate line; a plurality of top electrodes, each top electrode contacting an upper surface of a corresponding ferroelectric line; a plurality of local interconnects, each memory cell having a respective local interconnect in full contact with a top surface of its corresponding top electrode so that the top electrode is fully covered by the local interconnect, the local interconnect also extending laterally along the first direction and downward to make electrical contact with said second source/drain region via a first contact window, the local interconnect and first contact window being situated beneath a corresponding bit line, the local interconnect having a common lateral edge self-aligned with an edge of the corresponding top electrode; the plate lines, ferroelectric dielectric lines, and top electrodes forming a plurality of ferroelectric capacitors located substantially at each intersection of a said bit line and a said word line, the bit lines extending over the ferroelectric capacitors; wherein the plate lines, ferroelectric lines, bit lines, and word lines extend to respective pluralities of said memory cells.

Claim 25

The memory cell array of claim 22 wherein the top electrodes are local top electrodes located at discrete locations above said ferroelectric dielectric line, each said local top electrode being located in its corresponding memory cell only.

Claim 26

The memory cell array of claim 22 wherein each said top electrode and its corresponding local interconnect have respective first lateral edges that are substantially aligned with each other within each memory cell from having been etched together in a single step.

Claim 27

The memory cell array of claim 24 wherein, within each said memory cell, each said top electrode has a respective second lateral edge which is opposite and parallel to said first lateral edge; wherein each said local interconnect includes a second lateral edge; wherein said second lateral edges are laterally spaced apart; and wherein each said top electrode also includes third and fourth lateral edges parallel to each other and at an angle to said first and second lateral edges thereof.

Claim 28

The memory cell array of claim 22 wherein each said top electrode is generally centrally located over a corresponding word line.

Claim 29

The memory cell array of claim 22 wherein each said plate line, ferroelectric dielectric line, and top electrode are generally centrally located over the corresponding word line.

Claim 30

The memory cell array of claim 22 wherein, for each memory cell, the corresponding bit line extends through an etched contact opening over the first source/drain region to make said electrical contact therewith.

Claim 31

The memory cell array of claim 28 wherein said etched contact opening extends through a plurality of insulation layers.

Claim 32

The memory cell array of claim 29 wherein said plurality of insulation layers includes said first insulation layer which elsewhere in the memory cell covers the top of said word line and a second insulation layer which elsewhere in the memory cell insulates the local interconnect from the ferroelectric dielectric.

Claim 33

The memory cell array of claim 30 wherein said plurality of insulation layers further includes a third insulation layer which elsewhere in the memory cell insulates the local interconnect from the bit line; and wherein at said etched contact opening, said third insulation layer contacts a top of said second insulation layer, which contacts a top of said first insulation layer.

Claim 34

The memory cell array of claim 22 wherein, with reference to said first direction, each said plate line is as wide as its corresponding ferroelectric dielectric line, and wherein no side of said ferroelectric dielectric line in the memory cell extends beyond a side of the corresponding bottom electrode.

Claim 35

A compact memory cell arrangement for an integrated circuit where the memory cell includes a ferroelectric capacitor and a transistor, and where the cell is connected to a bit line, a word line, and a plate line, the arrangement comprising: a substrate; a bit line extending along a first direction, the bit line crossing over first and second source/drain regions in the substrate for the transistor, and making electrical contact with said first source/drain region; a word line extending along a second direction perpendicular to the first direction, the word line providing a gate electrode for the memory cell transistor; a first insulation layer on top of the substrate having a portion covering the top of the word line; a plate line extending parallel to the word line, but separated therefrom by the first insulation layer, the plate line constituting a bottom capacitor electrode in each memory cell through which it passes; a ferroelectric dielectric line parallel to and on top of the plate line; the plate line and the ferroelectric dielectric line being centrally located above the word line; wherein, with reference to said first direction, said plate line is as wide as said ferroelectric dielectric line; wherein no side of said ferroelectric dielectric line in the memory cell extends beyond a side of the bottom electrode; a second insulation layer having a portion located on top of the first insulation layer, and having another portion covering sides of the plate line and the ferroelectric dielectric line; a top electrode contacting an upper surface of the ferroelectric line; a local interconnect for the memory cell, the local interconnect being self-aligned to and extending laterally from a lateral edge of the top electrode along the first direction and downward to make electrical contact with said second source/drain region via a first contact window etched through the first and second insulation layers, the local interconnect being in full contact with and completely covering the top surface of the top electrode, the local interconnect and first contact window being situated beneath the bit line; the plate line, ferroelectric dielectric line, and the top electrode forming a ferroelectric capacitor substantially at the intersection of the bit line and the word line; wherein the bit line extends over the ferroelectric capacitor; a third insulation layer having a portion located on top of said second insulation layer having another portion located on top of said local interconnect; wherein said bit line extends through a second etched contact window located over first source/drain region to make said electrical contact therewith; said second etched contact window extending through said first, second, and third insulation layers; wherein the plate line, ferroelectric line, bit line, and word line extend to a plurality of other memory cells.

Claim 36

A compact memory cell arrangement for an integrated circuit where the memory cell includes a ferroelectric capacitor and a transistor, and where the cell is connected to a bit line, a word line, and a plate line, the arrangement comprising: a substrate; a bit line extending along a first direction, the bit line crossing over first and second source/drain regions in the substrate for the transistor, and making electrical contact with said first source/drain region; a word line extending along a second direction perpendicular to the first direction, the word line providing a gate electrode for the memory cell transistor; a first insulation layer on top of the substrate having a portion covering the top of the word line; a plate line extending parallel to the word line, but separated therefrom by the first insulation layer, the plate line constituting a bottom capacitor electrode in each memory cell through which it passes; a ferroelectric dielectric line parallel to and on top of the plate line; the plate line and the ferroelectric dielectric line being centrally located above the word line; wherein, with reference to said first direction, said plate line is as wide as said ferroelectric dielectric line; wherein no side of said ferroelectric dielectric line in the memory cell extends beyond a side of the bottom electrode; a second insulation layer having a portion located on top of the first insulation layer, and having another portion covering sides of the plate line and the ferroelectric dielectric line; a top electrode contacting an upper surface of the ferroelectric line; a local interconnect for the memory cell, the local interconnect being self-aligned to and extending laterally from a lateral edge of the top electrode along the first direction and downward to make electrical contact with said second source/drain region via a first contact window etched through the first and second insulation layers, the local interconnect being in full contact with and completely covering the top surface of the top electrode, the local interconnect and first contact window being situated beneath the bit line; the plate line, ferroelectric dielectric line, and the top electrode forming a ferroelectric capacitor substantially at the intersection of the bit line and the word line; wherein the bit line extends over the ferroelectric capacitor; a third insulation layer having a portion located on top of said second insulation layer having another portion located on top of said local interconnect; wherein said bit line extends through a second etched contact window located over first source/drain region to make said electrical contact therewith; said second etched contact window extending through said first, second, and third insulation layers; wherein the plate line, ferroelectric line, bit line, and word line extend to a plurality of other memory cells.

Claim 37

The memory cell arrangement of claim 33 wherein said top electrode is a local top electrode confined entirely below said bit line; wherein said top electrode contacts said ferroelectric line via a third contact window through said second insulation layer.