Integrated ferroelectric capacitor

Claim 2

A memory cell for use in an integrated circuit comprising: a switching device having a control electrode and first and second regions, with the conductivity between said two regions being responsive to a voltage applied to the control electrode; a bit line positioned to make electrical contact with said first region; a ferroelectric material positioned in said memory cell and coupled directly or indirectly to said second region; an electrode contacting said ferroelectric material and being spaced from said second region by said ferroelectric material whereby a ferroelectric capacitor is formed; and a further conductor coupled to said electrode.

Claim 3

The memory cell according to claim 1 wherein said switching device comprises a field effect transistor, wherein said ferroelectric material comprises PZT located over the source region in a contact window thereto, wherein said field effect transistor includes a drain region having a contact window thereto, the bit line contacting said drain region at said contact window.

Claim 4

The memory cell according to claim 2 wherein said field effect transistor includes a gate electrode, and said memory includes a word line, said word line forming said gate electrode.

Claim 5

The memory cell according to claim 3 wherein the source contact window is planarized by said ferroelectric material and top electrode.

Claim 6

A memory cell for use in an integrated circuit comprising: a transistor having source and drain regions and a gate electrode, said source and drain regions being formed in or upon a substrate; an insulator on the top and sides of said gate electrode; a source contact window located over said source region, and a drain contact window located over said drain region, said gate electrode insulator being located between said contact windows; a ferroelectric dielectric material located in said source contact window; an electrode material between said ferroelectric material and said source region; a first conductor located above said ferroelectric material and making electrical contact thereto, whereby a capacitor is formed over said source region; and a second conductor electrically coupled to said drain region via said drain contact window and forming a bit line.

Claim 7

A memory cell for use in an integrated circuit comprising: a transistor having source and drain regions and a gate electrode, said source and drain regions being formed in or upon a substrate; an insulator on the top and sides of said gate electrode; a source contact window located over said source region, and a drain contact window located over said drain region, said gate electrode insulator being located between said contact windows; a ferroelectric dielectric material located in said source contact window; an electrode material between said ferroelectric material and said source region; a first conductor located above said ferroelectric material and making electrical contact thereto, whereby a capacitor is formed over said source region; and a second conductor electrically coupled to said drain region via said drain contact window and forming a bit line.

Claim 8

The cell of claim 5 further comprising interlevel dielectric located over said first conductor, said gate electrode, said ferroelectric material and other portions of the substrate, said second conductor extending through said interlevel dielectric at said drain contact window, said second conductor generally planarizing said memory cell.