US5241201A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dram with concentric adjacent capacitors
Assignee: Panasonic Holdings Corp
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Filing: 1991-04-02
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Granted: 1993-08-31
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Expires: 2011-04-02
Abstract
Abstract A new semiconductor memory device for performing a read/write of information of randomly accessed address includes a plurality of memory cells put in parallel arrays. Each memory cell includes a switching transistor region and a capacitor region. The capacitor regions of the two adjacent memory cells are formed in a common region over the switching transistor region of the two adjacent memory cells. The charge storage electrode of the capacitor region has the shape of a loop. The charge storage electrodes are formed by using self-alignment.
Inventors
- 👤 Naoto Matsuo
- 👤 Shozo Okada
- 👤 Susumu Matsumoto
- 👤 Yoshiro Nakata
- 👤 Toshiki Yabu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:23
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
164 words
A semiconductor memory device including a semiconductor substrate having a primary surface, said semiconductor memory device having a plurality of memory cells, each said memory cell comprising: a switching transistor on said substrate, said switching transistor including a gate electrode connected to a word line, a drain electrode region connected to a bit line and a source electrode region; and a capacitor for storing information charges, said capacitor comprising a charge storage electrode connected to said source electrode region by a contact, said charge storage electrode extending perpendicularly to said primary surface of said substrate; said memory cells being arranged into pairs of adjacent memory cells; wherein the charge storage electrode of the capacitor of one memory cell of each adjacent pair of memory cells, viewed in a plane parallel to said primary surface, is in the shape of an at least partial loop surrounding the charge storage electrode of the capacitor of the other memory cell of each adjacent pair of memory cells.
Claim 2
Dependent Claim
164 words
A semiconductor memory device including a semiconductor substrate having a primary surface, said semiconductor memory device having a plurality of memory cells, each said memory cell comprising: a switching transistor on said substrate, said switching transistor including a gate electrode connected to a word line, a drain electrode region connected to a bit line and a source electrode region; and a capacitor for storing information charges, said capacitor comprising a charge storage electrode connected to said source electrode region by a contact, said charge storage electrode extending perpendicularly to said primary surface of said substrate; said memory cells being arranged into pairs of adjacent memory cells; wherein the charge storage electrode of the capacitor of one memory cell of each adjacent pair of memory cells, viewed in a plane parallel to said primary surface, is in the shape of an at least partial loop surrounding the charge storage electrode of the capacitor of the other memory cell of each adjacent pair of memory cells.
Claim 3
Dependent Claim
38 words
The semiconductor memory device of claim 1, wherein the charge storage electrode of the capacitor of said one memory cell defines a closed loop completely surrounding the charge storage electrode of the capacitor of said other memory cell.
Claim 4
Dependent Claim
39 words
The semiconductor memory device of claim 1, wherein the charge storage electrode of the capacitor of said one memory cell defines an open loop only partially surrounding the charge storage electrode of the capacitor of said other memory cell.
Claim 5
Dependent Claim
43 words
The semiconductor memory device of claim 1, wherein the charge storage electrodes of the capacitors of said one memory cell and said other memory cell are each in the form of a rectangle when viewed in a plane parallel to said primary surface.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-30 | 1997-03-01 | 1997-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-30 | 2001-03-01 | 2001-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-30 | 2005-03-01 | 2005-08-31 | $7700.00 | Window Closed / Lapsed |