US5227855A
Expired / Lapsed
US
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Semiconductor memory device having a ferroelectric substance as a memory element
Assignee: Toshiba Corp
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Filing: 1991-01-23
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Granted: 1993-07-13
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Expires: 2011-01-23
Abstract
Abstract An insulating layer is formed on a transistor having a source region/drain region and a gate electrode. Contact holes are formed in this insulating layer in association with the source region/drain region and the gate electrode. A memory element having a ferroelectric substance layer is provided in that contact hole which is associated with the source region/drain region. This memory element comprises a first electrode provided on the source region/drain region, a ferroelectric substance layer provided on the first electrode, and a second electrode provided on the ferroelectric substance layer. Providing this memory element in the contact hole which is associated with the source region/drain region can make cells flatter and permit metal wires to be surely formed in the contact holes.
Inventors
- 👤 Hisayo S. Momose
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:51
CPC Classifications
H; H10; H10B; H10B53/00
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
177 words
A semiconductor memory device comprising: a transistor having a gate electrode and a diffusion layer defining a source region and a drain region; an insulating layer on said transistor, said insulating layer defining a plurality of contact holes corresponding to said diffusion layer and to said gate electrode; a memory element in one of said contact holes corresponding to said diffusion layer, said memory element including a first electrode on said diffusion layer, the first electrode having a first major surface, a ferroelectric substance layer having a second major surface and a third major surface, the first and second major surfaces defining an interface that is parallel to the diffusion layer, a second electrode, the second electrode having a fourth major surface, the third and fourth major surfaces defining an interface that is parallel to the diffusion layer, a metal wire on the second electrode, wherein the gate electrode is located at a first level relative to the diffusion layer and the ferroelectric substance layer is located at a level substantially the same as the first level.
Claim 2
Dependent Claim
177 words
A semiconductor memory device comprising: a transistor having a gate electrode and a diffusion layer defining a source region and a drain region; an insulating layer on said transistor, said insulating layer defining a plurality of contact holes corresponding to said diffusion layer and to said gate electrode; a memory element in one of said contact holes corresponding to said diffusion layer, said memory element including a first electrode on said diffusion layer, the first electrode having a first major surface, a ferroelectric substance layer having a second major surface and a third major surface, the first and second major surfaces defining an interface that is parallel to the diffusion layer, a second electrode, the second electrode having a fourth major surface, the third and fourth major surfaces defining an interface that is parallel to the diffusion layer, a metal wire on the second electrode, wherein the gate electrode is located at a first level relative to the diffusion layer and the ferroelectric substance layer is located at a level substantially the same as the first level.
Claim 3
Dependent Claim
41 words
A device according to claim 1, wherein said memory element further comprises: a first silicon oxide film between said first electrode and said ferroelectric substance layer; and a second silicon oxide film between said ferroelectric substance layer and said second electrode.
Claim 4
Dependent Claim
174 words
An EEPROM comprising: a transistor having a gate electrode and a diffusion layer defining a source region and a drain region; an insulating layer on said transistor, said insulating layer defining a plurality of contact holes corresponding to said diffusion layer and said gate electrode; a memory element in one of said contact holes corresponding to said diffusion layer, said memory element including a first electrode on said diffusion layer, the first electrode having a first major surface, a ferroelectric substance layer having a second major surface and a third major surface, the first and second major surfaces defining an interface that is parallel to the diffusion layer, a second electrode, the second electrode having a fourth major surface, the third and fourth major surfaces defining an interface that is parallel to the diffusion layer a metal wire on the second electrode, wherein the gate electrode is located at a first level relative to the diffusion layer and the ferroelectric substance layer is located at a level substantially the same as the first level.
Claim 5
Dependent Claim
174 words
An EEPROM comprising: a transistor having a gate electrode and a diffusion layer defining a source region and a drain region; an insulating layer on said transistor, said insulating layer defining a plurality of contact holes corresponding to said diffusion layer and said gate electrode; a memory element in one of said contact holes corresponding to said diffusion layer, said memory element including a first electrode on said diffusion layer, the first electrode having a first major surface, a ferroelectric substance layer having a second major surface and a third major surface, the first and second major surfaces defining an interface that is parallel to the diffusion layer, a second electrode, the second electrode having a fourth major surface, the third and fourth major surfaces defining an interface that is parallel to the diffusion layer a metal wire on the second electrode, wherein the gate electrode is located at a first level relative to the diffusion layer and the ferroelectric substance layer is located at a level substantially the same as the first level.
Claim 6
Dependent Claim
61 words
A device according to claim 3, wherein said memory element comprises: a first electrode on said diffusion layer; a first silicon oxide film on said first electrode; a ferroelectric substance layer on said first silicon oxide film; a second silicon oxide film on said ferroelectric substance layer; and a second electrode on said silicon oxide film, connected to said metal wires.
Claim 7
Dependent Claim
199 words
An EEPROM using a memory element having a ferroelectric substance layer, comprising: a transistor having a gate electrode and a diffusion layer defining a source region and a drain region; an insulating layer on said transistor, said insulating layer defining a plurality of contact holes corresponding to said diffusion layer and to said gate electrode; a first electrode in a one of said contact holes corresponding to said diffusion layer, and adjoining to said diffusion layer, said first electrode having a first major surface; a ferroelectric substance layer in the one of the contact holes, the ferroelectric substance layer having a second major surface and a third major surface, the first and second major surfaces defining an interface that is parallel to the diffusion layer; a second electrode having a fourth major surface, the third and fourth major surfaces defining an interface that is parallel to the diffusion layer; and metal wires on said in said contact holes and on said insulating layer in said contact holes, wherein the gate electrode is located at a first level relative to the diffusion layer and the ferroelectric substance layer is located at a level substantially the same as the first level.
Claim 8
Dependent Claim
199 words
An EEPROM using a memory element having a ferroelectric substance layer, comprising: a transistor having a gate electrode and a diffusion layer defining a source region and a drain region; an insulating layer on said transistor, said insulating layer defining a plurality of contact holes corresponding to said diffusion layer and to said gate electrode; a first electrode in a one of said contact holes corresponding to said diffusion layer, and adjoining to said diffusion layer, said first electrode having a first major surface; a ferroelectric substance layer in the one of the contact holes, the ferroelectric substance layer having a second major surface and a third major surface, the first and second major surfaces defining an interface that is parallel to the diffusion layer; a second electrode having a fourth major surface, the third and fourth major surfaces defining an interface that is parallel to the diffusion layer; and metal wires on said in said contact holes and on said insulating layer in said contact holes, wherein the gate electrode is located at a first level relative to the diffusion layer and the ferroelectric substance layer is located at a level substantially the same as the first level.
Claim 9
Dependent Claim
132 words
An EEPROM using a memory element having a ferroelectric substance layer, comprising: a transistor having a diffusion layer as a source region/drain region and a gate electrode; an insulating layer on said transistor, said insulating layer defining a plurality of contact holes corresponding to said diffusion layer and to said gate electrode; a first electrode in one of said contact holes corresponding to said diffusion layer, said adjoining to said diffusion layer; a ferroelectric substance layer on said first electrode; a first silicon film on said first electrode; a ferroelectric substance layer on said first silicon film; a second silicon film on said ferroelectric substance layer; and a second electrode on said silicon film; and metal wires on said in said contact holes and on said insulating layer in said contact holes.
Claim 10
Dependent Claim
132 words
An EEPROM using a memory element having a ferroelectric substance layer, comprising: a transistor having a diffusion layer as a source region/drain region and a gate electrode; an insulating layer on said transistor, said insulating layer defining a plurality of contact holes corresponding to said diffusion layer and to said gate electrode; a first electrode in one of said contact holes corresponding to said diffusion layer, said adjoining to said diffusion layer; a ferroelectric substance layer on said first electrode; a first silicon film on said first electrode; a ferroelectric substance layer on said first silicon film; a second silicon film on said ferroelectric substance layer; and a second electrode on said silicon film; and metal wires on said in said contact holes and on said insulating layer in said contact holes.
Claim 11
Dependent Claim
106 words
A semiconductor memory device comprising: a transistor having a gate electrode and a diffusion layer defining a source region and a drain region; an insulating layer on the transistor, the insulating layer defining a plurality of contact holes corresponding to the diffusion layer and to the gate electrode; a memory element in one of the contact holes corresponding to the diffusion layer, the memory element including: a first electrode on the diffusion layer; a ferroelectric element having a ferroelectric substance layer and a silicon oxide film on the ferroelectric substance layer; a second electrode on the ferroelectric element, and a metal wire on the second electrode.
Claim 12
Dependent Claim
106 words
A semiconductor memory device comprising: a transistor having a gate electrode and a diffusion layer defining a source region and a drain region; an insulating layer on the transistor, the insulating layer defining a plurality of contact holes corresponding to the diffusion layer and to the gate electrode; a memory element in one of the contact holes corresponding to the diffusion layer, the memory element including: a first electrode on the diffusion layer; a ferroelectric element having a ferroelectric substance layer and a silicon oxide film on the ferroelectric substance layer; a second electrode on the ferroelectric element, and a metal wire on the second electrode.
Claim 13
Dependent Claim
106 words
A semiconductor memory device comprising: a transistor having a gate electrode and a diffusion layer defining a source region and a drain region; an insulating layer on the transistor, the insulating layer defining a plurality of contact holes corresponding to the diffusion layer and to the gate electrode; a memory element in one of the contact holes corresponding to the diffusion layer, the memory element including a first electrode on the diffusion layer, a silicon oxide film on the first electrode, a ferroelectric substance layer on the silicon oxide film, a second electrode on the ferroelectric substance layer, and a metal wire on the second electrode.
Claim 14
Dependent Claim
106 words
A semiconductor memory device comprising: a transistor having a gate electrode and a diffusion layer defining a source region and a drain region; an insulating layer on the transistor, the insulating layer defining a plurality of contact holes corresponding to the diffusion layer and to the gate electrode; a memory element in one of the contact holes corresponding to the diffusion layer, the memory element including a first electrode on the diffusion layer, a silicon oxide film on the first electrode, a ferroelectric substance layer on the silicon oxide film, a second electrode on the ferroelectric substance layer, and a metal wire on the second electrode.
Claim 15
Dependent Claim
106 words
A semiconductor memory device comprising: a transistor having a gate electrode and a diffusion layer defining a source region and a drain region; an insulating layer on the transistor, the insulating layer defining a plurality of contact holes corresponding to the diffusion layer and to the gate electrode; a memory element in one of the contact holes corresponding to the diffusion layer, the memory element including a first electrode on the diffusion layer a ferroelectric substance layer on the first electrode, a silicon oxide film on the ferroelectric substance layer, a second electrode on the silicon oxide film, and a metal wire on the second electrode.
Claim 16
Dependent Claim
106 words
A semiconductor memory device comprising: a transistor having a gate electrode and a diffusion layer defining a source region and a drain region; an insulating layer on the transistor, the insulating layer defining a plurality of contact holes corresponding to the diffusion layer and to the gate electrode; a memory element in one of the contact holes corresponding to the diffusion layer, the memory element including a first electrode on the diffusion layer a ferroelectric substance layer on the first electrode, a silicon oxide film on the ferroelectric substance layer, a second electrode on the silicon oxide film, and a metal wire on the second electrode.
Claim 17
Dependent Claim
36 words
A device according to claim 9, wherein the gate electrode is at a first level relative to the diffusion layer and the ferroelectric substance layer is at a level substantially the same as the first level.
Claim 18
Dependent Claim
36 words
A device according to claim 10, wherein the gate electrode is at a first level relative to the diffusion layer and the ferroelectric substance layer is at a level substantially the same as the first level.
Claim 19
Dependent Claim
36 words
A device according to claim 9, wherein the gate electrode is at a first level relative to the diffusion layer and the ferroelectric substance layer is at a level substantially the same as the first level.
Claim 20
Dependent Claim
22 words
A device according to claim 7, wherein the ferroelectric substance layer has a major surface that is parallel to the diffusion layer.
Claim 21
Dependent Claim
22 words
A device according to claim 8, wherein the ferroelectric substance layer has a major surface that is parallel to the diffusion layer.
Claim 22
Dependent Claim
22 words
A device according to claim 9, wherein the ferroelectric substance layer has a major surface that is parallel to the diffusion layer.
Claim 23
Dependent Claim
22 words
A device according to claim 10, wherein the ferroelectric substance layer has a major surface that is parallel to the diffusion layer.
Claim 24
Dependent Claim
22 words
A device according to claim 11, wherein the ferroelectric substance layer has a major surface that is parallel to the diffusion layer.
Claim 25
Dependent Claim
22 words
A device according to claim 12, wherein the ferroelectric substance layer has a major surface that is parallel to the diffusion layer.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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