US4149302A
Expired / Lapsed
US
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Monolithic semiconductor integrated circuit ferroelectric memory device
Assignee: Ferrosil Corp
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Filing: 1978-06-08
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Granted: 1979-04-17
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Expires: 1998-06-08
Abstract
Abstract An improved monolithic semiconductor integrated circuit-ferroelectric device is disclosed together with the method of manufacturing the same. It was found that the preferred ferroelectric material, namely Phase III potassium nitrate, is extremely sensitive to moisture requiring unique processing steps to fabricate the structure. The process of manfacturing the monolithic structure is multi-stepped and is particularly adapted for fabricating a potassium nitrate ferroelectric memory on a semiconductor integrated circuit.
Inventors
- 👤 Robert C. Cook
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 06:35
CPC Classifications
H; H10; H10B; H10B53/00; Y; Y10; Y10T; Y10T29/00; Y10T29/43; Y10T29/435; Y10T29/49; Y10T29/49002; Y10T29/4902; Y10T29/49069; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49146
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
87 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A. forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and forming interconnect and bonding pad vias therein; C. depositing a conductive layer and forming a bottom electrode; D. applying a ferroelectric layer; E. applying a conductive layer over the ferroelectric layer; F. removing the conductive layer and the ferroelectric layer in selected areas; and G. depositing another conductive layer and forming a top electrode.
Claim 2
Independent Claim
87 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A. forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and forming interconnect and bonding pad vias therein; C. depositing a conductive layer and forming a bottom electrode; D. applying a ferroelectric layer; E. applying a conductive layer over the ferroelectric layer; F. removing the conductive layer and the ferroelectric layer in selected areas; and G. depositing another conductive layer and forming a top electrode.
Claim 3
Dependent Claim
15 words
The method of claim 1 wherein said ferroelectric layer substantially comprises Phase III potassium nitrate.
Claim 4
Dependent Claim
15 words
The method of claim 1 wherein said first layer interconnects are composed of doped polysilicon.
Claim 5
Dependent Claim
26 words
The method of claim 1 wherein said non-semiconductor dielectric is selected from the group consisting of low temperature glass, silicon nitride, and sputtered and evaporated dielectrics.
Claim 6
Dependent Claim
15 words
The method of claim 1 wherein said first layer interconnects are composed of a metal.
Claim 7
Dependent Claim
27 words
The method of claim 2 wherein said Phase III potassium nitrate layer has a thickness within a range of from 100 angstrom units to 25,000 angstrom units.
Claim 8
Dependent Claim
26 words
The method of claim 2 wherein said Phase III potassium nitrate layer has a thickness of less than 2 micron and is stable at room temperature.
Claim 9
Independent Claim
116 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A. forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and cutting interconnect and bonding pad vias therein; C. depositing a conductive layer and forming a bottom electrode; D. depositing a second non-semiconductive dielectric and forming vias therein; E. applying a ferroelectric layer; F. applying a conductive layer over the ferroelectric layer; G. applying a photoresist over the conductive layer; H. removing the photoresist, conductive layer and ferroelectric layer in selected areas; I. removing the remaining photoresist to expose the remaining conductive layer; and J. depositing another conductive layer and forming a top electrode.
Claim 10
Independent Claim
116 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A. forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and cutting interconnect and bonding pad vias therein; C. depositing a conductive layer and forming a bottom electrode; D. depositing a second non-semiconductive dielectric and forming vias therein; E. applying a ferroelectric layer; F. applying a conductive layer over the ferroelectric layer; G. applying a photoresist over the conductive layer; H. removing the photoresist, conductive layer and ferroelectric layer in selected areas; I. removing the remaining photoresist to expose the remaining conductive layer; and J. depositing another conductive layer and forming a top electrode.
Claim 11
Dependent Claim
24 words
The method of claim 8 wherein the photoresist is hardened in image-wise configuration in areas over the vias formed in the second dielectric layer.
Claim 12
Dependent Claim
39 words
The method of claim 9 wherein the non-hardened photoresist and the conductive layer and ferroelectric layer located below the non-hardened photoresist are removed by a process selected from the group consisting of sputter etching, ion milling and plasma etching.
Claim 13
Dependent Claim
17 words
The method of claim 8 wherein a non-semiconductor dielectric layer is uniformily deposited over the top electrode.
Claim 14
Dependent Claim
16 words
The method of claim 8 wherein said ferroelectric layer substantially comprises a Phase III potassium nitrate.
Claim 15
Independent Claim
18 words
The method of claims 1 or 8 wherein conductive material is applied to the bonding and interconnect pads.
Claim 16
Independent Claim
131 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A. forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and cutting interconnect and bonding pad vias therein; C. depositing a conductive layer and forming a bottom electrode; D. depositing a second non-semiconductive dielectric and forming vias therein; E. applying a ferroelectric layer; F. applying a conductive layer over the ferroelectric layer; G. applying a photoresist over the conductive layer; H. removing the photoresist, conductive layer and ferroelectric layer in selected areas; I. removing the remaining photoresist to expose the remaining conductive layer; J. applying a third non-semiconductive dielectric layer and forming vias over the exposed conductive layer; and K. depositing another conductive layer and forming a top electrode.
Claim 17
Independent Claim
131 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A. forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and cutting interconnect and bonding pad vias therein; C. depositing a conductive layer and forming a bottom electrode; D. depositing a second non-semiconductive dielectric and forming vias therein; E. applying a ferroelectric layer; F. applying a conductive layer over the ferroelectric layer; G. applying a photoresist over the conductive layer; H. removing the photoresist, conductive layer and ferroelectric layer in selected areas; I. removing the remaining photoresist to expose the remaining conductive layer; J. applying a third non-semiconductive dielectric layer and forming vias over the exposed conductive layer; and K. depositing another conductive layer and forming a top electrode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-04-16 | 1982-10-16 | 1983-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-04-16 | 1986-10-16 | 1987-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-04-16 | 1990-10-16 | 1991-04-17 | $7700.00 | Window Closed / Lapsed |