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US6060402A
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Process for selective recess etching of epitaxial field effect transistors with a novel etch-stop layer
Assignee: MACOM Technology Solutions Holdings Inc
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Filing: 1998-07-23
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Granted: 2000-05-09
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Expires: 2018-07-23
Abstract
Abstract A process for selective recess etching of GaAs field-effect transistors. A selected etch stop layer (In x Ga 1-x P) maintains what is commonly referred to as lattice-match with the GaAs substrate material. By using this etch stop, a significant reduction in access resistances is realized with respect to devices containing other etch stop materials while an improvement in the uniformity of device characteristics across the wafer and from wafer to wafer is realized.
Inventors
- 👤 Allen W. Hanson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 10:16
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/015; H10P; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10P50/646
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
120 words
A process for fabricating a semiconductor device, the process comprising: growing an n-channel layer of GaAs on a buffer layer; growing a Schottky layer on said channel layer; epitaxially growing an etch-stop layer on said Schottky layer; growing first and second layers of GaAs on said etch-stop layer, said second layer being a highly doped contact layer; and selectively etching portions of said first and said second layers to form a gate region, said first and said second layers having a first etch rate, and said etch stop layer having a second etch rate in a chosen etch chemistry, with a ratio of said said first etch rate to said second etch rate being on the order of about 150.
Claim 2
Dependent Claim
120 words
A process for fabricating a semiconductor device, the process comprising: growing an n-channel layer of GaAs on a buffer layer; growing a Schottky layer on said channel layer; epitaxially growing an etch-stop layer on said Schottky layer; growing first and second layers of GaAs on said etch-stop layer, said second layer being a highly doped contact layer; and selectively etching portions of said first and said second layers to form a gate region, said first and said second layers having a first etch rate, and said etch stop layer having a second etch rate in a chosen etch chemistry, with a ratio of said said first etch rate to said second etch rate being on the order of about 150.
Claim 3
Dependent Claim
32 words
A process as recited in claim 1, wherein said etch stop layer is In x Ga 1-x P where x varies as a function of the thickness of said etch stop layer.
Claim 4
Dependent Claim
9 words
A process as recited in claim 2, wherein 0.4≦x≦0.6.
Claim 5
Dependent Claim
23 words
A process as recited in claim 1, wherein said etch chemistry is H 2 SO 4 :H 2 O 2 :H 2 O.
Claim 6
Dependent Claim
18 words
A process as recited in claim 1, wherein a gate metal layer is deposited in said gate region.
Claim 7
Dependent Claim
20 words
A process as recited in claim 2, wherein said etch-stop layer has a thickness on the order of 10-40 Angstroms.
Claim 8
Dependent Claim
39 words
A process as recited in claim 1, further comprising opening a window in said etch stop layer via a second etch chemistry and depositing a gate metal layer therein, said gate metal making electrical contact with said Schottky layer.
Claim 9
Dependent Claim
18 words
A process as recited in claim 7, wherein said second etch chemistry is HCl:H 3 PO 4 :HCl.
Claim 10
Dependent Claim
131 words
A process for fabricating a field-effect transistor, the process comprising: growing an epitaxial buffer layer of unintentionally doped GaAs on a GaAs substrate; growing an epitaxial n-channel layer on said buffer layer; growing a Schottky layer on said n-channel layer; growing an In x Ga 1-x P etch-stop layer on said n-channel layer where x varies as a function of the thickness of said etch stop layer; growing first and second layers of GaAs on said etch-stop layer; and selectively etching said first and second layers to form a recess in said first and second layers, said selective etching effected with an etch chemistry, said etch chemistry etching said first and second layers at a rate on the order of 150 times faster than said etch chemistry etches said etch-stop layer.
Claim 11
Dependent Claim
131 words
A process for fabricating a field-effect transistor, the process comprising: growing an epitaxial buffer layer of unintentionally doped GaAs on a GaAs substrate; growing an epitaxial n-channel layer on said buffer layer; growing a Schottky layer on said n-channel layer; growing an In x Ga 1-x P etch-stop layer on said n-channel layer where x varies as a function of the thickness of said etch stop layer; growing first and second layers of GaAs on said etch-stop layer; and selectively etching said first and second layers to form a recess in said first and second layers, said selective etching effected with an etch chemistry, said etch chemistry etching said first and second layers at a rate on the order of 150 times faster than said etch chemistry etches said etch-stop layer.
Claim 12
Dependent Claim
9 words
A process as recited in claim 9, wherein 0.4≦x≦0.6.
Claim 13
Dependent Claim
23 words
A process as recited in claim 9, wherein said etch chemistry is H 2 SO 4 :H 2 O 2 :H 2 O.
Claim 14
Dependent Claim
18 words
A process as recited in claim 9, wherein a gate metal layer is deposited in said gate region.
Claim 15
Dependent Claim
20 words
A process as recited in claim 9, wherein said etch-stop layer has a thickness on the order of 10-40 Angstroms.
Claim 16
Dependent Claim
39 words
A process as recited in claim 9, further comprising opening a window in said etch stop layer via a second etch chemistry and depositing a gate metal layer therein, said gate metal making electrical contact with said Schottky layer.
Claim 17
Dependent Claim
18 words
A process as recited in claim 14, wherein said second etch chemistry is HCl:H 3 PO 4 :HCl.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2003-05-09 | 2003-11-08 | 2004-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-09 | 2007-11-08 | 2008-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-09 | 2011-11-08 | 2012-05-09 | $7700.00 | Window Closed / Lapsed |