High electron mobility transistor with an improved interface between donor and schottky layers

Claim 2

A semiconductor multi-layer structure comprising: a channel layer made of a first compound semiconductor having a first conduction band edge level, said channel layer being doped with an impurity and having a first thickness sufficient for confining a two-dimensional electron gas; a donor layer overlying said channel layer, said donor layer being made of a second compound semiconductor having a second conduction band edge level higher than said first conduction band edge level, said donor layer being doped with an impurity, said donor layer being sufficiently thin for allowing electrons to show a tunneling across said donor layer; a single quantum well layer overlying said donor layer, said quantum well layer being made of a third compound semiconductor having a third conduction band edge level lower than said second conduction band edge level, said single quantum well layer being sufficiently thin for preventing any formation of a two-dimensional electron gas; a Schottky barrier layer overlying said single quantum well layer, said Schottky barrier layer being made of a fourth compound semiconductor having a fourth conduction band edge level higher than said third conduction band edge level, said Schottky barrier layer being sufficiently thin for allowing electrons to show a tunneling across said Schottky barrier layer; and a cap layer overlying said Schottky barrier layer, said cap layer being made of a fifth compound semiconductor having a fifth conduction band edge level lower than said fourth conduction band edge level, said cap layer being doped with an impurity, so that when a bias is applied between said channel layer and said cap layer, electrons move between said channel layer and said cap layer via tunnelings across said Schottky barrier layer and across said donor layer.

Claim 3

The structure as claimed in claim 1, wherein said donor layer has a thickness not more than 500 angstroms.

Claim 4

The structure as claimed in claim 1, wherein said Shottky barrier layer has a thickness not more than 500 angstroms.

Claim 5

The structure as claimed in claim 1, wherein said single quantum well layer has a thickness not more than 150 angstroms.

Claim 6

The structure as claimed in claim 1, wherein said first compound semiconductor is one selected from the group consisting of lnGaAs and GaAs.

Claim 7

The structure as claimed in claim 1, wherein said second compound semiconductor is one selected from the group consisting of InAlAs and InGaP.

Claim 8

The structure as claimed in claim 1, wherein said second compound semiconductor is one selected from the group consisting of AlGaAs, InAlAs, InAlSb and InGaSb.

Claim 9

The structure as claimed in claim 1, wherein said third compound semiconductor is one selected from the group consisting of InGaAs, GaAs, InP, InGaP, InGaSb, and InAlSbP.

Claim 10

The structure as claimed in claim 8, wherein said fourth compound semiconductor is one selected from the group consisting of InAlAs and AlGaAs.

Claim 11

The structure as claimed in claim 1, wherein said fifth compound semiconductor is one selected from the group consisting of InGaAs, GaAs and InAs.

Claim 12

A semiconductor multi-layer structure comprising: a channel layer made of a first compound semiconductor having a first conduction band edge level, said channel layer being doped with an impurity and having a first thickness sufficient for confining a two-dimensional electron gas; a donor layer overlying said channel layer, said donor layer being made of a second compound semiconductor having a second conduction band edge level higher than said first conduction band edge level, said donor layer being doped with an impurity, said donor layer being sufficiently thin for allowing electrons to show a tunneling across said donor layer; a multiple-quantum well layer structure overlying said donor layer, said multiple-quantum well layer structure comprising at least two quantum well layers and at least one potential barrier layer sandwiched between said quantum well layers, said potential barrier layer being made of said second compound semiconductor, said quantum well layers being made of a third compound semiconductor having a third conduction band edge level lower than said second conduction band edge level, each of said quantum well layers being sufficiently thin for preventing any formation of a two-dimensional electron gas, and said potential barrier layer being sufficiently thin for allowing electrons to show a tunneling across said potential barrier layer; a Schottky barrier layer overlying the top one of said quantum well layers, said Schottky barrier layer being made of a fourth compound semiconductor having a fourth conduction band edge level higher than said third conduction band edge level, said Schottky barrier layer being sufficiently thin for allowing electrons to show a tunneling across said Schottky barrier layer; and a cap layer overlying said Schottky barrier layer, said cap layer being made of a fifth compound semiconductor having a fifth conduction band edge level lower than said fourth conduction band edge level, so that when a bias is applied between said channel layer and said cap layer, electrons move between said channel layer and said cap layer via tunnelings across said Schottky barrier layer, across said donor layer and across said potential barrier layer.

Claim 13

A semiconductor multi-layer structure comprising: a channel layer made of a first compound semiconductor having a first conduction band edge level, said channel layer being doped with an impurity and having a first thickness sufficient for confining a two-dimensional electron gas; a donor layer overlying said channel layer, said donor layer being made of a second compound semiconductor having a second conduction band edge level higher than said first conduction band edge level, said donor layer being doped with an impurity, said donor layer being sufficiently thin for allowing electrons to show a tunneling across said donor layer; a multiple-quantum well layer structure overlying said donor layer, said multiple-quantum well layer structure comprising at least two quantum well layers and at least one potential barrier layer sandwiched between said quantum well layers, said potential barrier layer being made of said second compound semiconductor, said quantum well layers being made of a third compound semiconductor having a third conduction band edge level lower than said second conduction band edge level, each of said quantum well layers being sufficiently thin for preventing any formation of a two-dimensional electron gas, and said potential barrier layer being sufficiently thin for allowing electrons to show a tunneling across said potential barrier layer; a Schottky barrier layer overlying the top one of said quantum well layers, said Schottky barrier layer being made of a fourth compound semiconductor having a fourth conduction band edge level higher than said third conduction band edge level, said Schottky barrier layer being sufficiently thin for allowing electrons to show a tunneling across said Schottky barrier layer; and a cap layer overlying said Schottky barrier layer, said cap layer being made of a fifth compound semiconductor having a fifth conduction band edge level lower than said fourth conduction band edge level, so that when a bias is applied between said channel layer and said cap layer, electrons move between said channel layer and said cap layer via tunnelings across said Schottky barrier layer, across said donor layer and across said potential barrier layer.

Claim 14

The structure as claimed in claim 11, wherein said donor layer has a thickness not more than 500 angstroms.

Claim 15

The structure as claimed in claim 11, wherein said Shottky barrier layer has a thickness not more than 500 angstroms.

Claim 16

The structure as claimed in claim 11, wherein said potential barrier layer has a thickness not more than 500 angstroms.

Claim 17

The structure as claimed in claim 11, wherein each of said quantum well layers has a thickness not more than 150 angstroms.

Claim 18

The structure as claimed in claim 11, wherein said first compound semiconductor is one selected from the group consisting of InGaAs and GaAs.

Claim 19

The structure as claimed in claim 11, wherein said second compound semiconductor is one selected from the group consisting of InAlAs and InGaP.

Claim 20

The structure as claimed in claim 11, wherein said second compound semiconductor is one selected from the group consisting of AlGaAs, InAlAs, InAlSb and InGaSb.

Claim 21

The structure as claimed in claim 11, wherein said third compound semiconductor is one selected from the group consisting of InGaAs, GaAs, InP, InGaP, InGaSb, and InAlSbP.

Claim 22

The structure as claimed in claim 19, wherein said fourth compound semiconductor is one selected from the group consisting of InAlAs and AlGaAs.

Claim 23

The structure as claimed in claim 11, wherein said fifth compound semiconductor is one selected from the group consisting of InGaAs, GaAs and InAs.

Claim 24

A high electron mobility field effect transistor comprising: a channel layer overlying a semiconductor substrate, said channel layer being made of a first compound semiconductor having a first conduction band edge level, said channel layer being doped with an impurity and having a first thickness sufficient for confining a two-dimensional electron gas; a donor layer overlying said channel layer, said donor layer being made of a second compound semiconductor having a second conduction band edge level higher than said first conduction band edge level, said donor layer being doped with an impurity, said donor layer being sufficiently thin for allowing electrons to show a tunneling across said donor layer; a single quantum well layer overlying said donor layer, said quantum well layer being made of a third compound semiconductor having a third conduction band edge level lower than said second conduction band edge level, said single quantum well layer being sufficiently thin for preventing any formation of a two-dimensional electron gas; a Schottky barrier layer overlying said single quantum well layer, said Schottky barrier layer being made of a fourth compound semiconductor having a fourth conduction band edge level higher than said third conduction band edge level, said Schottky barrier layer being sufficiently thin for allowing electrons to show a tunneling across said Schottky barrier layer; and a cap layer with a recessed portion overlying said Schottky barrier layer, said cap layer being made of a fifth compound semiconductor having a fifth conduction band edge level lower than said fourth conduction band edge level, said cap layer being doped with an impurity, a Schottky gate electrode provided in said recessed portion of said cap layer so as to be spaced apart from said cap layer; and source/drain electrodes provided on said cap layer, so that when a bias is applied between said source/drain electrodes, electrons move between said channel layer and said cap layer via tunnelings across said Schottky barrier layer and across said donor layer.

Claim 25

A high electron mobility field effect transistor comprising: a channel layer overlying a semiconductor substrate, said channel layer being made of a first compound semiconductor having a first conduction band edge level, said channel layer being doped with an impurity and having a first thickness sufficient for confining a two-dimensional electron gas; a donor layer overlying said channel layer, said donor layer being made of a second compound semiconductor having a second conduction band edge level higher than said first conduction band edge level, said donor layer being doped with an impurity, said donor layer being sufficiently thin for allowing electrons to show a tunneling across said donor layer; a single quantum well layer overlying said donor layer, said quantum well layer being made of a third compound semiconductor having a third conduction band edge level lower than said second conduction band edge level, said single quantum well layer being sufficiently thin for preventing any formation of a two-dimensional electron gas; a Schottky barrier layer overlying said single quantum well layer, said Schottky barrier layer being made of a fourth compound semiconductor having a fourth conduction band edge level higher than said third conduction band edge level, said Schottky barrier layer being sufficiently thin for allowing electrons to show a tunneling across said Schottky barrier layer; and a cap layer with a recessed portion overlying said Schottky barrier layer, said cap layer being made of a fifth compound semiconductor having a fifth conduction band edge level lower than said fourth conduction band edge level, said cap layer being doped with an impurity, a Schottky gate electrode provided in said recessed portion of said cap layer so as to be spaced apart from said cap layer; and source/drain electrodes provided on said cap layer, so that when a bias is applied between said source/drain electrodes, electrons move between said channel layer and said cap layer via tunnelings across said Schottky barrier layer and across said donor layer.

Claim 26

The transistor as claimed in claim 22, wherein said donor layer has a thickness not more than 500 angstroms.

Claim 27

The transistor as claimed in claim 22, wherein said Shottky barrier layer has a thickness not more than 500 angstroms.

Claim 28

The transistor as claimed in claim 22, wherein said single quantum well layer has a thickness not more than 150 angstroms.

Claim 29

The transistor as claimed in claim 22, wherein said first compound semiconductor is one selected from the group consisting of InGaAs and GaAs.

Claim 30

The transistor as claimed in claim 22, wherein said second compound semiconductor is one selected from the group consisting of InAlAs and InGaP.

Claim 31

The transistor as claimed in claim 22, wherein said second compound semiconductor is one selected from the group consisting of AlGaAs, InAlAs, InAlSb and InGaSb.

Claim 32

The transistor as claimed in claim 22, wherein said third compound semiconductor is one selected from the group consisting of InGaAs, GaAs, InP, InGaP, InGaSb, and InAlSbP.

Claim 33

The transistor as claimed in claim 29, wherein said fourth compound semiconductor is one selected from the group consisting of InAlAs and AlGaAs.

Claim 34

The transistor as claimed in claim 22, wherein said fifth compound semiconductor is one selected from them group consisting of InGaAs, GaAs and InAs.

Claim 35

The transistor as claimed in claim 22, further comprising a buffer layer between said semiconductor substrate and said channel layer, said buffer layer being made of a sixth compound semiconductor having a sixth conduction band edge level higher than said first conduction band edge level.

Claim 36

The transistor as claimed in claim 32, wherein said sixth compound semiconductor is one selected from the group consisting of i-InAlAs and i-InP.

Claim 37

The transistor as claimed in claim 22, further comprising an additional donor layer between said semiconductor substrate and said channel layer, said additional donor layer being made of a seventh compound semiconductor having a seventh conduction band edge level higher than said first conduction band edge level, and said additional donor layer being doped with an impurity.

Claim 38

The transistor as claimed in claim 22, wherein said source/drain electrodes are made of Ti/Pt/Au.

Claim 39

The transistor as claimed in claim 22, wherein said source/drain electrodes are made of WSi.

Claim 40

The transistor as claimed in claim 22, wherein said source/drain electrodes are made of Mo.

Claim 41

A high electron mobility field effect transistor comprising: a channel layer overlying a semiconductor substrate, said channel layer being made of a first compound semiconductor having a first conduction band edge level, said channel layer being doped with an impurity and having a first thickness sufficient for confining a two-dimensional electron gas; a donor layer overlying said channel layer, said donor layer being made of a second compound semiconductor having a second conduction band edge level higher than said first conduction band edge level, said donor layer being doped with an impurity, said donor layer being sufficiently thin for allowing electrons to show a tunneling across said donor layer; a multiple-quantum well layer structure overlying said donor layer, said multiple-quantum well layer structure comprising at least two quantum well layers and at least one potential barrier layer sandwiched between said quantum well layers, said potential barrier layer being made of said second compound semiconductor, said quantum well layers being made of a third compound semiconductor having a third conduction band edge level lower than said second conduction band edge level, each of said quantum well layers being sufficiently thin for preventing any formation of a two-dimensional electron gas, and said potential barrier layer being sufficiently thin for allowing electrons to show a tunneling across said potential barrier layer; a Schottky barrier layer overlying the top one of said quantum well layers, said Schottky barrier layer being made of a fourth compound semiconductor having a fourth conduction band edge level higher than said third conduction band edge level, said Schottky barrier layer being sufficiently thin for allowing electrons to show a tunneling across said Schottky barrier layer; a cap layer overlying said Schottky barrier layer, said cap layer being made of a fifth compound semiconductor having a fifth conduction band edge level lower than said fourth conduction band edge level; a Schottky gate electrode provided in said recessed portion of said cap layer so as to be spaced apart from said cap layer; and source/drain electrodes provided on said cap layer, so that when a bias is applied between said channel layer and said cap layer, electrons move between said channel layer and said cap layer via tunnelings across said Schottky barrier layer, across said donor layer and across said potential barrier layer.

Claim 42

A high electron mobility field effect transistor comprising: a channel layer overlying a semiconductor substrate, said channel layer being made of a first compound semiconductor having a first conduction band edge level, said channel layer being doped with an impurity and having a first thickness sufficient for confining a two-dimensional electron gas; a donor layer overlying said channel layer, said donor layer being made of a second compound semiconductor having a second conduction band edge level higher than said first conduction band edge level, said donor layer being doped with an impurity, said donor layer being sufficiently thin for allowing electrons to show a tunneling across said donor layer; a multiple-quantum well layer structure overlying said donor layer, said multiple-quantum well layer structure comprising at least two quantum well layers and at least one potential barrier layer sandwiched between said quantum well layers, said potential barrier layer being made of said second compound semiconductor, said quantum well layers being made of a third compound semiconductor having a third conduction band edge level lower than said second conduction band edge level, each of said quantum well layers being sufficiently thin for preventing any formation of a two-dimensional electron gas, and said potential barrier layer being sufficiently thin for allowing electrons to show a tunneling across said potential barrier layer; a Schottky barrier layer overlying the top one of said quantum well layers, said Schottky barrier layer being made of a fourth compound semiconductor having a fourth conduction band edge level higher than said third conduction band edge level, said Schottky barrier layer being sufficiently thin for allowing electrons to show a tunneling across said Schottky barrier layer; a cap layer overlying said Schottky barrier layer, said cap layer being made of a fifth compound semiconductor having a fifth conduction band edge level lower than said fourth conduction band edge level; a Schottky gate electrode provided in said recessed portion of said cap layer so as to be spaced apart from said cap layer; and source/drain electrodes provided on said cap layer, so that when a bias is applied between said channel layer and said cap layer, electrons move between said channel layer and said cap layer via tunnelings across said Schottky barrier layer, across said donor layer and across said potential barrier layer.

Claim 43

The transistor as claimed in claim 38, wherein said donor layer has a thickness not more than 500 angstroms.

Claim 44

The transistor as claimed in claim 38, wherein said Shottky barrier layer has a thickness not more than 500 angstroms.

Claim 45

The transistor as claimed in claim 38, wherein said potential barrier layer has a thickness not more than 500 angstroms.

Claim 46

The transistor as claimed in claim 38, wherein each of said quantum well layers has a thickness not more than 150 angstroms.

Claim 47

The transistor as claimed in claim 38, wherein said first compound semiconductor is one selected from the group consisting of InGaAs and GaAs.

Claim 48

The transistor as claimed in claim 38, wherein said second compound semiconductor is one selected from the group consisting of InAlAs and InGaP.

Claim 49

The transistor as claimed in claim 38, wherein said second compound semiconductor is one selected from the group consisting of AlGaAs, InAlAs, InAlSb and InGaSb.

Claim 50

The transistor as claimed in claim 38, wherein said third compound semiconductor is one selected from the group consisting of InGaAs, GaAs, InP, InGaP, InGaSb, and InAlSbP.

Claim 51

The transistor as claimed in claim 46, wherein said fourth compound semiconductor is one selected from the group consisting of InAlAs and AlGaAs.

Claim 52

The transistor as claimed in claim 38, wherein said fifth compound semiconductor is one selected from the group consisting of InGaAs, GaAs and InAs.

Claim 53

The transistor as claimed in claim 38, further comprising a buffer layer between said semiconductor substrate and said channel layer, said buffer layer being made of a sixth compound semiconductor having a sixth conduction band edge level higher than said first conduction band edge level.

Claim 54

The transistor as claimed in claim 49, wherein said sixth compound semiconductor is one selected from the group consisting of i-InAlAs and i-InP.

Claim 55

The transistor as claimed in claim 38, further comprising an additional donor layer between said semiconductor substrate and said channel layer, said additional donor layer being made of a seventh compound semiconductor having a seventh conduction band edge level higher than said first conduction band edge level, and said additional donor layer being doped with an impurity.

Claim 56

The transistor as claimed in claim 38, wherein said source/drain electrodes are made of Ti/Pt/Au.

Claim 57

The transistor as claimed in claim 38, wherein said source/drain electrodes are made of WSi.

Claim 58

The transistor as claimed in claim 38, wherein said source/drain electrodes are made of Mo.

Claim 59

A semiconductor multi-layer structure comprising: a channel layer made of a first compound semiconductor having a first conduction band edge level, said channel layer being doped with an impurity and having a first thickness sufficient for confining a two-dimensional electron gas; a donor layer overlying said channel layer, said donor layer being made of a second compound semiconductor having a second conduction band edge level higher than said first conduction band edge level, said donor layer being doped with an impurity, said donor layer being sufficiently thin for allowing electrons to show a tunneling across said donor layer; a single quantum well layer overlying said donor layer, said quantum well layer being made of a third compound semiconductor having a third conduction band edge level lower than said second conduction band edge level, said single quantum well layer being sufficiently thin for preventing any formation of a two-dimensional electron gas; a Schottky barrier layer overlying said single quantum well layer, said Schottky barrier layer being made of a fourth compound semiconductor having a fourth conduction band edge level higher than said third conduction band edge level, said Schottky barrier layer being undoped, and said Schottky barrier layer being sufficiently thin for allowing electrons to show a tunneling across said Schottky barrier layer; and a cap layer overlying said Schottky barrier layer, said cap layer being made of a fifth compound semiconductor having a fifth conduction band edge level lower than said fourth conduction band edge level, said cap layer being doped with an impurity, so that when a bias is applied between said channel layer and said cap layer, electrons move between said channel layer and said cap layer via tunnelings across said Schottky barrier layer and across said donor layer, wherein said fourth compound semiconductor has an electron affinity which is substantially equal to that of said second compound semiconductor so that a conduction band edge profile of said Schottky barrier layer is substantially aligned on a straight line which extends from a conduction band edge profile of said donor layer in the vicinity of an interface between said single quantum well layer and said donor layer.

Claim 60

A semiconductor multi-layer structure comprising: a channel layer made of a first compound semiconductor having a first conduction band edge level, said channel layer being doped with an impurity and having a first thickness sufficient for confining a two-dimensional electron gas; a donor layer overlying said channel layer, said donor layer being made of a second compound semiconductor having a second conduction band edge level higher than said first conduction band edge level, said donor layer being doped with an impurity, said donor layer being sufficiently thin for allowing electrons to show a tunneling across said donor layer; a single quantum well layer overlying said donor layer, said quantum well layer being made of a third compound semiconductor having a third conduction band edge level lower than said second conduction band edge level, said single quantum well layer being sufficiently thin for preventing any formation of a two-dimensional electron gas; a Schottky barrier layer overlying said single quantum well layer, said Schottky barrier layer being made of a fourth compound semiconductor having a fourth conduction band edge level higher than said third conduction band edge level, said Schottky barrier layer being undoped, and said Schottky barrier layer being sufficiently thin for allowing electrons to show a tunneling across said Schottky barrier layer; and a cap layer overlying said Schottky barrier layer, said cap layer being made of a fifth compound semiconductor having a fifth conduction band edge level lower than said fourth conduction band edge level, said cap layer being doped with an impurity, so that when a bias is applied between said channel layer and said cap layer, electrons move between said channel layer and said cap layer via tunnelings across said Schottky barrier layer and across said donor layer, wherein said fourth compound semiconductor has an electron affinity which is substantially equal to that of said second compound semiconductor so that a conduction band edge profile of said Schottky barrier layer is substantially aligned on a straight line which extends from a conduction band edge profile of said donor layer in the vicinity of an interface between said single quantum well layer and said donor layer.

Claim 61

The structure as claimed in claim 55, wherein said donor layer has a thickness not more than 500 angstroms, wherein said Schottky barrier layer has a thickness not more than 500 angstroms, and wherein said single quantum well layer has a thickness not more than 150 angstroms.

Claim 62

The structure as claimed in claim 55, wherein said first compound semiconductor is one selected from the group consisting of InGaAs, GaAs, wherein said second compound semiconductor is one selected from the group consisting of InAlAs, InGaP, AlGaAs, InAlSb and InGaSb, wherein said third compound semiconductor is one selected from the group consisting of InGaAs, GaAs, InP, InGaP, InGaSb, and InAlSbP, wherein said fourth compound semiconductor is one selected from the group consisting of InAlAs and AlGaAs, and wherein said fifth compound semiconductor is one selected from the group consisting of InGaAs, GaAs and InAs.

Claim 63

A semiconductor multi-layer structure comprising: a channel layer made of a first compound semiconductor having a first conduction band edge level, said channel layer being doped with an impurity and having a first thickness sufficient for confining a two-dimensional electron gas; a donor layer overlying said channel layer, said donor layer being made of a second compound semiconductor having a second conduction band edge level higher than said first conduction band edge level, said donor layer being doped with an impurity, said donor layer being sufficiently thin for allowing electrons to show a tunneling across said donor layer; a multiple-quantum well layer structure overlying said donor layer, said multiple-quantum well layer structure comprising at least two quantum well layers and at least one potential barrier layer sandwiched between said quantum well layers, said potential barrier layer being made of said second compound semiconductor, said quantum well layers being made of a third compound semiconductor having a third conduction band edge level lower than said second conduction band edge level, each of said quantum well layers being sufficiently thin for preventing any formation of a two-dimensional electron gas, and said potential barrier layer being sufficiently thin for allowing electrons to show a tunneling across said potential barrier layer; a Schottky barrier layer overlying the top one of said quantum well layers said Schottky barrier layer being made of a fourth compound semiconductor having a fourth conduction band edge level higher than said third conduction band edge level, said Schottky barrier layer being undoped, and said Schottky barrier layer being sufficiently thin for allowing electrons to show a tunneling across said Schottky barrier layer; and a cap layer overlying said Schottky barrier layer, said cap layer being made of a fifth compound semiconductor having a fifth conduction band edge level lower than said fourth conduction band edge level, so that when a bias is applied between said channel layer and said cap layer, electrons move between said channel layer and said cap layer via tunnelings across said Schottky barrier layer, across said donor layer and across said potential barrier layer, wherein said fourth compound semiconductor has an electron affinity which is substantially equal to that of said second compound semiconductor so that a conduction band edge profile of said Schottky barrier layer is substantially aligned on a straight line which extends from a conduction band edge profile of said donor layer in the vicinity of an interface between said multiple-quantum well layer structure and said donor layer.

Claim 64

A semiconductor multi-layer structure comprising: a channel layer made of a first compound semiconductor having a first conduction band edge level, said channel layer being doped with an impurity and having a first thickness sufficient for confining a two-dimensional electron gas; a donor layer overlying said channel layer, said donor layer being made of a second compound semiconductor having a second conduction band edge level higher than said first conduction band edge level, said donor layer being doped with an impurity, said donor layer being sufficiently thin for allowing electrons to show a tunneling across said donor layer; a multiple-quantum well layer structure overlying said donor layer, said multiple-quantum well layer structure comprising at least two quantum well layers and at least one potential barrier layer sandwiched between said quantum well layers, said potential barrier layer being made of said second compound semiconductor, said quantum well layers being made of a third compound semiconductor having a third conduction band edge level lower than said second conduction band edge level, each of said quantum well layers being sufficiently thin for preventing any formation of a two-dimensional electron gas, and said potential barrier layer being sufficiently thin for allowing electrons to show a tunneling across said potential barrier layer; a Schottky barrier layer overlying the top one of said quantum well layers said Schottky barrier layer being made of a fourth compound semiconductor having a fourth conduction band edge level higher than said third conduction band edge level, said Schottky barrier layer being undoped, and said Schottky barrier layer being sufficiently thin for allowing electrons to show a tunneling across said Schottky barrier layer; and a cap layer overlying said Schottky barrier layer, said cap layer being made of a fifth compound semiconductor having a fifth conduction band edge level lower than said fourth conduction band edge level, so that when a bias is applied between said channel layer and said cap layer, electrons move between said channel layer and said cap layer via tunnelings across said Schottky barrier layer, across said donor layer and across said potential barrier layer, wherein said fourth compound semiconductor has an electron affinity which is substantially equal to that of said second compound semiconductor so that a conduction band edge profile of said Schottky barrier layer is substantially aligned on a straight line which extends from a conduction band edge profile of said donor layer in the vicinity of an interface between said multiple-quantum well layer structure and said donor layer.

Claim 65

The structure as claimed in claim 58, wherein said donor layer has a thickness not more than 500 angstroms, wherein said Schottky barrier layer has a thickness not more than 500 angstroms, wherein said potential barrier layer has a thickness not more than 500 angstroms, and wherein each of said quantum well layers has a thickness not more than 150 angstroms.

Claim 66

The structure as claimed in claim 58, wherein said first compound semiconductor is one selected from the group consisting of InGaAs and GaAs, wherein said second compound semiconductor is one selected from the group consisting of InAlAs, InGaP, AlGaAs, InAlSb and InGaSb, wherein said third compound semiconductor is one selected from the group consisting of InGaAs, GaAs, InP, InGaP, InGaSb, and InAlSbP, wherein said fourth compound semiconductor is one selected from the group consisting of InAlAs and AlGaAs, and wherein said fifth compound semiconductor is one selected from the group of InGaAs, GaAs and InAs.

Claim 67

A high electron mobility field effect transistor comprising: a channel layer overlying a semiconductor substrate, said channel layer being made of a first compound semiconductor having a first conduction band edge level, said channel layer being doped with an impurity and having a first thickness sufficient for confining a two-dimensional electron gas; a donor layer overlying said channel layer, said donor layer being made of a second compound semiconductor having a second conduction band edge level higher than said first conduction band edge level, said donor layer being doped with an impurity, said donor layer being sufficiently thin for allowing electrons to show a tunneling across said donor layer; a single quantum well layer overlying said donor layer; said quantum well layer being made of a third compound semiconductor having a third conduction band edge level lower than said second conduction band edge level, said single quantum well layer being sufficiently thin for preventing any formation of a two-dimensional electron gas; a Schottky barrier layer overlying said single quantum well layer, said Schottky barrier layer being made of a fourth compound semiconductor having a fourth conduction band edge level higher than said third conduction band edge level, said Schottky barrier layer being undoped, and said Schottky barrier layer being sufficiently thin for allowing electrons to show a tunneling across said Schottky barrier layer; and a cap layer with a recessed portion overlying said Schottky barrier layer, said cap layer being made of a fifth compound semiconductor having a fifth conduction band edge level lower than said fourth conduction band edge level, said cap layer being doped with an impurity, a Schottky gate electrode provided in said recessed portion of said cap layer so as to be spaced apart from said cap layer; and source/drain electrodes provided on said cap layer, so that when a bias is applied between said source/drain electrodes, electrons move between said channel layer and said cap layer via tunnelings across said Schottky barrier layer and across said donor layer, wherein said fourth compound semiconductor has an electron affinity which is substantially equal to that of said second compound semiconductor so that a conduction band edge profile of said Schottky barrier layer is substantially aligned on a straight line which extends from a conduction band edge profile of said donor layer in the vicinity of an interface between said single quantum well layer and said donor layer.

Claim 68

A high electron mobility field effect transistor comprising: a channel layer overlying a semiconductor substrate, said channel layer being made of a first compound semiconductor having a first conduction band edge level, said channel layer being doped with an impurity and having a first thickness sufficient for confining a two-dimensional electron gas; a donor layer overlying said channel layer, said donor layer being made of a second compound semiconductor having a second conduction band edge level higher than said first conduction band edge level, said donor layer being doped with an impurity, said donor layer being sufficiently thin for allowing electrons to show a tunneling across said donor layer; a single quantum well layer overlying said donor layer; said quantum well layer being made of a third compound semiconductor having a third conduction band edge level lower than said second conduction band edge level, said single quantum well layer being sufficiently thin for preventing any formation of a two-dimensional electron gas; a Schottky barrier layer overlying said single quantum well layer, said Schottky barrier layer being made of a fourth compound semiconductor having a fourth conduction band edge level higher than said third conduction band edge level, said Schottky barrier layer being undoped, and said Schottky barrier layer being sufficiently thin for allowing electrons to show a tunneling across said Schottky barrier layer; and a cap layer with a recessed portion overlying said Schottky barrier layer, said cap layer being made of a fifth compound semiconductor having a fifth conduction band edge level lower than said fourth conduction band edge level, said cap layer being doped with an impurity, a Schottky gate electrode provided in said recessed portion of said cap layer so as to be spaced apart from said cap layer; and source/drain electrodes provided on said cap layer, so that when a bias is applied between said source/drain electrodes, electrons move between said channel layer and said cap layer via tunnelings across said Schottky barrier layer and across said donor layer, wherein said fourth compound semiconductor has an electron affinity which is substantially equal to that of said second compound semiconductor so that a conduction band edge profile of said Schottky barrier layer is substantially aligned on a straight line which extends from a conduction band edge profile of said donor layer in the vicinity of an interface between said single quantum well layer and said donor layer.

Claim 69

The transistor as claimed in claim 61, wherein said donor layer has a thickness not more than 500 angstroms, wherein said Schottky barrier layer has a thickness not more than 500 angstroms, and wherein said single quantum well layer has a thickness not more than 150 angstroms.

Claim 70

The transistor as claimed in claim 61, wherein said first compound semiconductor is one selected from the group consisting of InGaAs and GaAs, wherein said second compound semiconductor is one selected from the group consisting of InAlAs, InGaP, AlGaAs, InAlSb and InGaSb, wherein said third compound semiconductor is one selected from the group consisting of InGaAs, GaAs, InP, InGaP, InGaSb, and InAlSbP, wherein said fourth compound semiconductor is one selected from the group consisting of InAlAs and AlGaAs, and wherein said fifth compound semiconductor is one selected from the group consisting of InGaAs, GaAs and InAs.

Claim 71

The transistor as claimed in claim 55, further comprising a buffer layer between said semiconductor substrate and said channel layer, said buffer layer being made of a sixth compound semiconductor having a sixth conduction band edge level higher than said first conduction band edge level.

Claim 72

The transistor as claimed in claim 64, wherein said sixth compound semiconductor is one selected from the group consisting of i-InAlAs and i-InP.

Claim 73

The transistor as claimed in claim 61, further comprising an additional donor layer between said semiconductor substrate and said channel layer, said additional donor layer being made of a seventh compound semiconductor having a seventh conduction band edge level higher than said first conduction band edge level, and said additional donor layer being doped with an impurity.

Claim 74

The transistor as claimed in claim 22, wherein said source/drain electrodes are made of one selected from the group consisting of Ti/Pt/Au, Wsi and Mo.

Claim 75

A high electron mobility field effect transistor comprising: a channel layer overlying a semiconductor substrate, said channel layer being made of a first compound semiconductor having a first conduction band edge level, said channel layer being doped with an impurity and having a first thickness sufficient for confining a two-dimensional electron gas; a donor layer overlying said channel layer, said donor layer being made of a second compound semiconductor having a second conduction band edge level higher than said first conduction band edge level, said donor layer being doped with an impurity, said donor layer being sufficiently thin for allowing electrons to show a tunneling across said donor layer; a multiple-quantum well layer structure overlying said donor layer, said multiple-quantum well layer structure comprising at least two quantum well layers and at least one potential barrier layer sandwiched between said quantum well layers, said potential barrier layer being made of said second compound semiconductor, said quantum well layers being made of a third compound semiconductor having a third conduction band edge level lower than said second conduction band edge level, each of said quantum well layers being sufficiently thin for preventing any formation of a two-dimensional electron gas, and said potential barrier layer being sufficiently thin for allowing electrons to show a tunneling across said potential barrier layer; a Schottky barrier layer overlying the top one of said quantum well layers, said Schottky barrier layer being made of a fourth compound semiconductor having a fourth conduction band edge level higher than said third conduction band edge level, said Schottky barrier layer being undoped, and said Schottky barrier layer being sufficiently thin for allowing electrons to show a tunneling across said Schottky barrier layer; a cap layer overlying said Schottky barrier layer, said cap layer being made of a fifth compound semiconductor having a fifth conduction band edge level lower than said fourth conduction band edge level; a Schottky gate electrode provided in said recessed portion of said cap layer so as to be spaced apart from said cap layer; and source/drain electrodes provided on said cap layer, so that when a bias is applied between said channel layer and said cap layer, electrons move between said channel layer and said cap layer via tunnelings across said Schottky barrier layer, across said donor layer and across said potential barrier layer, wherein said fourth compound semiconductor has an electron affinity which is substantially equal to that of said second compound semiconductor so that a conduction band edge profile of said Schottky barrier layer is substantially aligned on a straight line which extends from a conduction band edge profile of said donor layer in the vicinity of an interface between said multiple-quantum well layer structure and said donor layer.

Claim 76

A high electron mobility field effect transistor comprising: a channel layer overlying a semiconductor substrate, said channel layer being made of a first compound semiconductor having a first conduction band edge level, said channel layer being doped with an impurity and having a first thickness sufficient for confining a two-dimensional electron gas; a donor layer overlying said channel layer, said donor layer being made of a second compound semiconductor having a second conduction band edge level higher than said first conduction band edge level, said donor layer being doped with an impurity, said donor layer being sufficiently thin for allowing electrons to show a tunneling across said donor layer; a multiple-quantum well layer structure overlying said donor layer, said multiple-quantum well layer structure comprising at least two quantum well layers and at least one potential barrier layer sandwiched between said quantum well layers, said potential barrier layer being made of said second compound semiconductor, said quantum well layers being made of a third compound semiconductor having a third conduction band edge level lower than said second conduction band edge level, each of said quantum well layers being sufficiently thin for preventing any formation of a two-dimensional electron gas, and said potential barrier layer being sufficiently thin for allowing electrons to show a tunneling across said potential barrier layer; a Schottky barrier layer overlying the top one of said quantum well layers, said Schottky barrier layer being made of a fourth compound semiconductor having a fourth conduction band edge level higher than said third conduction band edge level, said Schottky barrier layer being undoped, and said Schottky barrier layer being sufficiently thin for allowing electrons to show a tunneling across said Schottky barrier layer; a cap layer overlying said Schottky barrier layer, said cap layer being made of a fifth compound semiconductor having a fifth conduction band edge level lower than said fourth conduction band edge level; a Schottky gate electrode provided in said recessed portion of said cap layer so as to be spaced apart from said cap layer; and source/drain electrodes provided on said cap layer, so that when a bias is applied between said channel layer and said cap layer, electrons move between said channel layer and said cap layer via tunnelings across said Schottky barrier layer, across said donor layer and across said potential barrier layer, wherein said fourth compound semiconductor has an electron affinity which is substantially equal to that of said second compound semiconductor so that a conduction band edge profile of said Schottky barrier layer is substantially aligned on a straight line which extends from a conduction band edge profile of said donor layer in the vicinity of an interface between said multiple-quantum well layer structure and said donor layer.

Claim 77

The transistor as claimed in claim 68, wherein said donor layer has a thickness not more than 500 angstroms, wherein said Schottky barrier layer has a thickness not more than 500 angstroms, wherein said potential barrier layer has a thickness not more than 500 angstroms, and wherein each of said quantum well layers has a thickness not more than 150 angstroms.

Claim 78

The transistor as claimed in claim 68, wherein said first compound semiconductor is one selected from the group consisting of InGaAs and GaAs, wherein said second compound semiconductor is one selected from the group consisting of InAlAs, InGaP, AlGaAs, InAlSb and InGaSb, wherein said third compound semiconductor is one selected from the group consisting of InGaAs, GaAs, InP, InGaP, InGaSb, and InAlSbP, wherein said fourth compound semiconductor is one selected from the group consisting of InAlAs and AlGaAs, and wherein said fifth compound semiconductor is one selected from the group consisting of InGaAs, GaAs and InAs.

Claim 79

The transistor as claimed in claim 68, further comprising a buffer layer between said semiconductor substrate and said channel layer, said buffer layer being made of a sixth compound semiconductor having a sixth conduction band edge level higher than said first conduction band edge level.

Claim 80

The transistor as claimed in claim 71, wherein said sixth compound semiconductor is one selected from the group consisting of i-InAlAs and i-InP.

Claim 81

The transistor as claimed in claim 68, further comprising an additional donor layer between said semiconductor substrate and said channel layer, said additional donor layer being made of a seventh compound semiconductor having a seventh conduction band edge level higher than said first conduction band edge level, and said additional donor layer being doped with an impurity.

Claim 82

The transistor as claimed in claim 68, wherein said source/drain electrodes are made of one selected from the group consisting of Ti/Pt/Au, Wsi and Mo.